Methods for predicting reliability of semiconductor devices using voltage stressing
AssigneeAdaptec, Inc.
InventorArnie London
Life of this patent
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AssigneeAdaptec, Inc.
InventorArnie London
Estimating the term…
Disclosed are methods for predicting reliability of semiconductor devices and wafers without a lengthy burn-in process. A set of semiconductor devices is obtained for testing. Each semiconductor device is capable of being electrically tested to measure one or more critical parameters that indicate potential failure of associated semiconductor device. On each of the semiconductor devices, a set of electrical tests is performed to obtain a failure result for the critical parameter(s) of each of the semiconductor devices. The set of electrical tests is performed both before and after stressing each of the semiconductor devices with an elevated voltage above a normal operating voltage for the semiconductor devices. For the set of semiconductor devices, a failure rate is determined from the failure results of the semiconductor devices. The failure rate indicates a probability of failure for the entire set of semiconductor devices.
A method for predicting reliability of semiconductor devices without undergoing a burn-in process, comprising:
A method for evaluating a failure rate of semiconductor wafers containing a plurality of semiconductor devices, comprising:
A method for evaluating a failure rate of a wafer lot having a set of semiconductor wafers, each semiconductor wafer containing a plurality of semiconductor devices, the method comprising:
Dependencies are inferred from the claim text.