Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

A method of fabricating a double gate MOSFET device comprising the steps of:

• a) providing a silicon on insulator (SOI) substrate with a first undoped silicon layer overlying an insulating layer and having an exposed major surface,
• b) providing an etchant mask on the major surface,
• c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,
• d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer,
• e) forming a gate dielectric on sidewalls of the channel region,
• f) depositing gate material over the etchant mask and the gate dielectric,
• g) selectively masking and etching the gate material to form a gate on the sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask,
• h) forming dielectric spacers between the gate and the source and drain regions, and
• i) doping the source and drain regions.

A method of fabricating a double gate MOSFET device comprising the steps of:

• a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface,
• b) providing an etchant mask on the major surface,
• c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,
• d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer,
• e) forming a gate dielectric on sidewalls of the channel region,
• f) depositing gate material over the etchant mask and the gate dielectric,
• g) selectively masking and etching the gate material to form a gate on the sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask, and forming a lightly doped drain extension in the channel between the gate and the drain region,
• h) forming dielectric spacers between the gate and the source and drain regions, and
• i) doping the source and drain regions.

A method of fabricating a double gate MOSFET device comprising the steps of:

• a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface,
• b) providing an etchant mask on the major surface,
• c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,
• d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer,
• e) forming a gate dielectric on sidewalls of the channel region,
• f) depositing undoped polysilicon gate material over the etchant mask and the gate dielectric,
• g) selectively masking and etching the gate material to form a gate on the sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask,
• h) forming dielectric spacers between the gate and the source and drain regions, and
• i) doping the gate, source and drain regions.

A method of fabricating a double gate MOSFET device comprising the steps of:

• a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface,
• b) providing an etchant mask on the major surface,
• c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,
• d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer,
• e) forming a gate dielectric on sidewalls of the channel region,
• f) depositing gate material over the etchant mask and the gate dielectric,
• g) selectively masking and etching the gate material to form a gate on the sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask,
• h) forming dielectric spacers between the gate and the source and drain regions, and
• i) doping the source and drain regions by angled shallow ion implantation to limit amorphizing the source and drain regions.

A method of fabricating a double gate MOSFET device comprising the steps of:

• a) providing a silicon on insulator (SOI) substrate with a first silicon layer overlying an insulating layer and having an exposed major surface,
• b) providing an etchant mask on the major surface,
• c) patterning the etchant mask to define source, drain, and channel regions and expose surrounding portions of the silicon layer,
• d) etching the exposed silicon layer and forming source, drain, and channel regions extending from the insulator layer,
• e) forming a gate dielectric on sidewalls of the channel region,
• f) depositing gate material over the etchant mask and the gate dielectric,
• g) selectively masking and etching the gate material to form a gate on the sidewalls of the channel region and separated from the channel region by the gate dielectric and the etchant mask,
• h) forming dielectric spacers between the gate and the source and drain regions,
• i) doping the source and drain regions, and
• j) applying conductive straps across and in contact with the source and drain regions.

A method of fabricating a double gate CMOS device comprising the steps of:

• a) providing a silicon on insulator (SOI) substrate with a first silicon layer over a dielectric layer and having an exposed major surface,
• b) selectively doping regions of the first silicon layer to accommodate source and drain regions of a first transistor,
• c) forming a second dielectric layer over the first silicon layer,
• d) forming a second silicon layer over the second dielectric layer,
• e) providing an etchant mask over the second silicon layer,
• f) patterning the etchant mask to define source, drain, and channel regions of two stacked transistors including the first transistor,
• g) etching the first and second silicon layers and the first and second dielectric layers thereby forming source, drain, and channel regions of the two stacked transistors,
• h) forming a gate dielectric on sidewalls of the channel regions,
• i) depositing gate material over the etchant mask and the gate dielectric,
• j) selectively masking and etching the gate material to form a gate on the sidewalls of the channel regions separated from the channel regions by the gate dielectric and the etchant mask, and
• k) doping the source and drain regions in the second silicon layer.

A method of fabricating a double gate CMOS device comprising the steps of:

• a) providing a silicon on insulator (SOI) substrate with a first silicon layer over a dielectric layer and having an exposed major surface,
• b) selectively doping regions of the first silicon layer to accommodate source and drain regions of a first transistor,
• c) forming a second dielectric layer over the first silicon layer,
• d) forming a second silicon layer over the second dielectric layer,
• e) providing an etchant mask over the second silicon layer,
• f) patterning the etchant mask to define source, drain, and channel regions of two stacked transistors,
• g) etching the first and second silicon layers and the first and second dielectric layers thereby forming source, drain, and channel regions of the two stacked transistors,
• h) forming a gate dielectric on sidewalls of the channel regions,
• i) depositing undoped polysilicon gate material over the etchant mask and the gate dielectric,
• j) selectively masking and etching the gate material to form a gate on the sidewalls of the channel regions separated from the channel regions by the gate dielectric and the etchant mask, and
• k) doping the gate, source and drain regions in the second silicon layer.

A double gate MOSFET device comprising:

• a) a silicon substrate having a dielectric layer on a major surface,
• b) a silicon source region and a silicon drain region with a channel region therebetween extending from the dielectric layer, the channel being a fin with a top surface and two opposing sidewalls,
• c) a gate dielectric layer on sidewalls of the channel region and an etchant mask overlying a top of the channel region, and
• d) a gate extending over the top and sidewalls of the channel region and electrically isolated therefrom by the gate dielectric and etchant mask.

A double gate MOSFET device comprising:

• a) a silicon substrate having a dielectric layer on a major surface,
• b) a silicon source region and a silicon drain region with a channel region therebetween extending from the dielectric layer,
• c) a gate dielectric layer on sidewalls of the channel region and an etchant mask overlying a top of the channel region, the etchant mask being selected from the group consisting of silicon oxide, silicon nitride, and combinations thereof, and
• d) a gate extending over the top and sidewalls of the channel region and electrically isolated therefrom by the gate dielectric and etchant mask.

A double gate MOSFET device comprising

• a) a silicon substrate having a dielectric layer on a major surface,
• b) a silicon source region and a silicon drain region with a plurality of channel regions between the source region and the drain region and extending from the dielectric layer,
• c) a gate dielectric layer on sidewalls of the channel region and an etchant mask overlying a top of the channel region, and
• d) a gate extending over the top and sidewalls of the channel region and electrically isolated therefrom by the gate dielectric and etchant mask.

A double gate CMOS device comprising:

• a) a silicon substrate having a dielectric layer on a major surface,
• b) a first silicon source region and a first silicon drain region with a first channel region therebetween extending from the dielectric layer,
• c) a second silicon source region and a second silicon drain region with a second channel region therebetween overlying the first silicon source region and the first silicon drain region and the first channel region with a dielectric therebetween,
• d) a gate dielectric on sidewalls of the channel regions and an etchant mask overlying a top of the second channel region, and
• e) a gate extending over the top and sidewalls of the channel regions and electrically isolated therefrom by the gate dielectric and etchant mask.