Semiconductor memory having transistors connected in series
AssigneeKabushiki Kaisha Toshiba
InventorsKoji Sakui, Mitsuhiro Noguchi
Life of this patent
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Abstract
A memory cell array is comprised of plural cell units. Each cell unit is connected between a bit line and a source line. Each cell unit is comprised of plural series-connected MFSFETs having substantially the same structure. Of the plural MFSFETs, one MFSFET nearest to the bit line and one MFSFET nearest to the source line are used as select gate transistors. The MFSFETs other than the MFSFETs used as the select gate transistors are used as memory cells. Data is stored in each memory cell as the polarization state of the ferroelectric film of the MFSFET.
Claims31
A semiconductor memory comprising:
- a cell unit having first and second ends and constituted by transistors connected in series between the first and second ends;
- a data transferring line connected to the first end of said cell unit;
- and
- a common voltage node connected to the second end of said cell unit,
- wherein each transistor has substantially the same structure and a function of storing data in a nonvolatile manner, one of the transistors which is located nearest to said data transferring line and one of the transistors which is located nearest to said common voltage node are used as select gate transistors, and the transistors other than the transistors used as the select gate transistors are used as memory cells.
A semiconductor memory comprising:
- a cell unit having first and second ends and constituted by MFSFETs connected in series between the first and second ends and having substantially the same structure;
- a data transferring line connected to the first end of said cell unit;
- and
- a common voltage node connected to the second end of said cell unit,
- wherein one of the MFSFETs which is located nearest to said data transferring line and one of the MFSFETs which is located nearest to said common voltage node are used as select gate transistors, and the MFSFETs other than the MFSFETs used as the select gate transistors are used as memory cells.
A semiconductor memory comprising:
- memory cells formed on a semiconductor region and connected in series or parallel between first and second nodes;
- and
- a select switching element formed on the semiconductor region and connected between the first node and a third node,
- wherein said memory cells and said select switching element each have a charge storing layer, and the charge storing layer of each of said memory cells is made of the same material as that for the charge storing layer of said select switching element and has the same thickness as that thereof.
A threshold voltage setting method of a semiconductor memory including a select gate transistor having a charge storing layer and memory cells having a charge storing layer, comprising the steps of:
- setting both a threshold voltage of the select gate transistor and a threshold voltage of the memory cells to be negative by erase operation;
- setting the threshold voltage of the select gate transistor to be positive by write operation;
- verifying whether the threshold voltage of the select gate transistor become positive;
- performing re-write operation if the threshold voltage of the select gate transistor has not become positive;
- setting the threshold voltage of the select gate transistor to be positive, and then performing write operation to make the threshold voltage of the select gate transistor fall within a set range;
- verifying whether the threshold voltage of the select gate transistor falls within the set range;
- and
- performing the re-write operation if the threshold voltage of the select gate transistor has not fallen within the set range.
Dependencies are inferred from the claim text.