Low jitter external clocking

A semiconductor die comprising:

• a data line to receive a data signal;
• a first clock signal line and a second clock signal line to receive a differential clock signal that is synchronized with the data signal;
• a first differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a first single-ended clock signal;
• a second differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a second single-ended clock signal;
• an inverter having an input coupled to the first differential amplifier to receive the first single-ended clock signal and to invert the first single-ended clock signal at an output;
• and
• a voltage follower having an input coupled to the second differential amplifier to receive the second single-ended clock signal and an output connected to the output of the inverter to generate a single-ended output clock signal.

A system comprising:

• a first circuit;
• a second circuit;
• a communication link coupled between the first circuit and the second circuit, the communication link comprising:
• a data bus coupled to receive a plurality of data signals from the second circuit;
• and
• a first clock signal line and a second clock signal line coupled to receive a differential clock signal from the second circuit that is synchronized with the data signals;
• a receiver circuit in the first circuit comprising:
• a first differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a first single-ended clock signal;
• a second differential amplifier coupled to the first clock signal line and the second clock signal line to amplify the differential clock signal into a second single-ended clock signal;
• an inverter having an input coupled to the first differential amplifier to receive the first single-ended clock signal and to invert the first single-ended clock signal at an output;
• and
• a voltage follower having an input coupled to the second differential amplifier to receive the second single-ended clock signal and an output connected to the output of the inverter to generate a single-ended output clock signal.

A method comprising:

• receiving a data signal on a data line;
• receiving a differential clock signal on a first clock signal line and a second clock signal line that is synchronized with the data signal;
• amplifying the differential clock signal into a single-ended clock signal in a first differential amplifier having a non-inverting input coupled to the first clock signal line and an inverting input coupled to the second clock signal line;
• amplifying the differential clock signal into a single-ended clock signal in a second differential amplifier having an inverting input coupled to the first clock signal line and a non-inverting input coupled to the second clock signal line;
• inverting one of the single-ended clock signals to generate an inverted single-ended clock signal;
• and
• combining the inverted single-ended clock signal with the single-ended clock signal that is not inverted to generate a single-ended output clock signal.

A method comprising:

• receiving a data signal on a data line;
• receiving a differential clock signal on a first clock signal line and a second clock signal line that is synchronized with the data signal;
• amplifying the differential clock signal into a first single-ended clock signal in a first differential amplifier coupled to the first clock signal line and the second clock signal line;
• amplifying the differential clock signal into a second single-ended clock signal in a second differential amplifier coupled to the first clock signal line and the second clock signal line;
• inverting the first single-ended clock signal in an inverter to generate an inverted single-ended clock signal;
• and
• combining the inverted single-ended clock signal with the second single-ended clock signal buffered by a voltage follower to generate a single-ended output clock signal.

A method comprising:

• transmitting data signals from a first circuit to a second circuit over a data bus;
• generating a differential clock signal in the first circuit that is synchronized with the data signals;
• transmitting the differential clock signal over a first clock signal line and a second clock signal line to the second circuit;
• and
• amplifying the differential clock signal in a differential clock signal receiver circuit in the second circuit comprising:
• amplifying the differential clock signal into a first single-ended clock signal in a first differential amplifier coupled to the first clock signal line and the second clock signal line;
• amplifying the differential clock signal into a second single-ended clock signal in a second differential amplifier coupled to the first clock signal line and the second clock signal line;
• inverting the first single-ended clock signal in an inverter to generate an inverted single-ended clock signal;
• and
• combining the inverted single-ended clock signal with the second single-ended clock signal buffered by a voltage follower to generate a single-ended output clock signal.
• 21.The method of claim 20 wherein amplifying the differential clock signal into a second single-ended clock signal further comprises amplifying the differential clock signal into a second single-ended clock signal that is 180 degrees out of phase with the first single-ended clock signal.

A system comprising:

• a plurality of circuits;
• a very high frequency common clock generator coupled to each of the circuits to generate a very high frequency clock signal;
• a plurality of communication links, each circuit being coupled to one or more neighboring circuits by one of the communication links, each communication link comprising:
• a data bus;
• a first differential clock signal line comprising two lines and coupled to carry a very high frequency differential clock signal in a first direction;
• and
• a second differential clock signal line comprising two lines and coupled to carry a very high frequency differential clock signal in a second direction;
• a differential clock signal generating circuit in each circuit coupled to one or more of the differential clock signal lines in one or more of the communication links to generate a very high frequency differential clock signal;
• and
• a receiver circuit in each circuit to receive one of the very high frequency differential clock signals, the receiver circuit comprising:
• a first differential amplifier coupled to one of the differential clock signal lines to amplify one of the very high frequency differential clock signals into a first single-ended clock signal;
• a second differential amplifier coupled to the differential clock signal line to amplify the very high frequency differential clock signal into a second single-ended clock signal;
• an inverter having an input coupled to the first differential amplifier to receive the first single-ended clock signal and to invert the first single-ended clock signal at an output;
• and
• a voltage follower having an input coupled to the second differential amplifier to receive the second single-ended clock signal and an output connected to the output of the inverter to generate a single-ended output clock signal.