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US 6,410,958 B1Granted
Power MOSFET having laterally three-layered structure formed among element isolation regions
AssigneeKabushiki Kaisha Toshiba
InventorsYasunori Usui, Shigeo Kouzuki
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Abstract
A semiconductor apparatus has an NPN (or PNP) laterally three-layered pillar formed in a mesh form among a plurality of trench type element isolation regions, and having a source and gate on an upper surface of the three-layered pillar, and a drain on a lower surface thereof. A depth DT and minimum planar width WTmin of the element isolation region and a width WP of the three-layered pillar are configured to satisfy a relation of 3.75≦DT/WP≦60 or 5.5≦DT/WTmin≦14.3. The above configuration realizes a high breakdown voltage and low on-resistance are realized.
Claims20
A semiconductor apparatus comprising:
- a semiconductor substrate of a first conductivity type having a first main surface and a second main surface;
- a plurality of element isolation regions each formed to have a predetermined depth DT from said first main surface of said semiconductor substrate, and formed by filling a plurality of trenches with an insulator;
- a laterally three-layered pillar formed among said plurality of element isolation regions with a width WP and in a meshed planar shape, said three-layered pillar including a first pillar layer and a second pillar layer each being of said first conductivity type which contact two adjacent element isolation regions out of said plurality of element isolation regions over a depth direction, respectively, said three-layered pillar including a third pillar layer of a second conductivity type formed between said first pillar layer and said second pillar layer, and said three-layered pillar having a relation of 3.75≦DT/WP≦60 between said width WP of said three-layered pillar and said depth DT of each of said plurality of element isolation regions;
- a base region of said second conductivity type formed on an upper surface of said third pillar layer of said second conductivity type;
- a source region of said first conductivity type selectively formed on an upper surface of said base region;
- a gate electrode formed on said base region between said source region and an upper surface of said first pillar layer or said second pillar layer in an insulating manner;
- and
- a drain layer of said first conductivity type formed on said second main surface of said semiconductor substrate, and contacting a lower surface of said three-layered pillar.
5 more elements
A semiconductor apparatus comprising:
- a semiconductor substrate of a first conductivity type having a first main surface and a second main surface;
- a plurality of element isolation regions each formed to have a predetermined depth DT from said first main surface of said semiconductor substrate, and formed by filling a plurality of trenches with an insulator;
- a laterally three-layered pillar formed among said plurality of element isolation regions with a width WP and in a meshed planar shape, so as to have a plurality of openings having a minimum opening width WTmin, said three-layered pillar including a first pillar layer and a second pillar layer each being of said first conductivity type which contact two adjacent element isolation regions out of said plurality of element isolation regions over a depth direction, respectively, said three-layered pillar including a third pillar layer of a second conductivity type formed between said first pillar layer and said second pillar layer, and said three-layered pillar having a relation of 5.5≦DT/WTmin≦14.3 between said minimum opening width WTmin of said three-layered pillar and said depth DT of each element isolation region of said plurality of element isolation regions;
- a base region of said second conductivity type formed on an upper surface of said third pillar layer of said second conductivity type;
- a source region of said first conductivity type selectively formed on an upper surface of said base region;
- a gate electrode formed on said base region between said source region and an upper surface of said first pillar layer or said second pillar layer in an insulating manner;
- and
- a drain layer of said first conductivity type formed on said second main surface of said semiconductor substrate, and contacting a lower surface of said three-layered pillar.
5 more elements
A semiconductor apparatus comprising:
- a semiconductor substrate of a first conductivity type having a first main surface and a second main surface;
- a plurality of element isolation regions each formed to have a predetermined depth DT from said first main surface of said semiconductor substrate, and formed by filling a plurality of trenches with an insulator;
- a laterally three-layered pillar formed among said plurality of element isolation regions with a width WP and in a meshed planar shape so as to have a plurality of openings having a minimum opening width WTmin, said three-layered pillar including a first pillar layer and a second pillar layer each being of said first conductivity type which contact two adjacent element isolation regions out of said plurality of element isolation regions over a depth direction, respectively, and said three-layered pillar including a third pillar layer of a second conductivity type formed between said first pillar layer and said second pillar layer;
- a base region of said second conductivity type formed on an upper surface of said third pillar layer of said second conductivity type;
- a source region of said first conductivity type selectively formed on an upper surface of said base region;
- a gate electrode formed on said base region between said source region and an upper surface of said first pillar layer or said second pillar layer in an insulating manner;
- and
- a drain layer of said first conductivity type formed on said second main surface of said semiconductor substrate, and contacting a lower surface of said three-layered pillar, wherein said plurality of element isolation regions include an edge termination isolation region surrounding a region with said three-layered pillar formed therein, and a relation with said minimum opening width WTmin of said three-layered pillar of said meshed planar shape satisfies WTEmin≧WTmin, wherein a minimum opening width of one of said plurality of trenches corresponding to said edge termination isolation region is WTEmin.
5 more elements
Dependencies are inferred from the claim text.