Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
AssigneeInternational Business Machines Corporation
InventorsClaude Louis Bertin, Wayne John Howell, William R. Tonti, Jerzy Maria Zalesinski
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Abstract
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections in a semiconductor package is disclosed. A semiconductor device has active devices on the front surface, a first through-chip conductor having first electrical/physical characteristics passing from the front surface of the device to the back surface, a second through-chip conductor having second electrical/physical characteristics passing to the back surface, and an off-chip or chip-to-chip connector electrically connecting the active devices on the front surface to a different level of packaging.
Claims6
A method of electrically and thermally connecting a semiconductor device having a front surface with active devices and a back surface to a different level of packaging, comprising:
- (a) providing at least one first through-chip conductor and at least one second through-chip conductor;
- (b) electrically passing a first characteristic through the first through-chip conductor, from said active devices of said semiconductor device to said different level of packaging, wherein the first characteristic comprises an electrical/physical characteristic;
- and
- (c) passing a second characteristic through the second through-chip conductor to said back surface of said semiconductor device, wherein the second characteristic comprises a thermal characteristic;
- wherein said step b) further comprises the steps of:
- b1) providing at least one chip connector;
- and
- b2) electrically connecting said active devices of said semiconductor device to said different level of packaging with said chip connector;
- wherein said step b1) further comprises:
- 1) depositing a first sacrificial layer on said semiconductor device;
- 2) etching a pair of first via holes in said first sacrificial layer;
- 3) plating a first conductive material in at least one of said first via holes;
- 4) depositing a second sacrificial layer on said first sacrificial layer;
- 5) etching a second via hole in said second sacrificial layer, wherein said second via hole connects with at least one of said first via holes;
- 6) plating a second conductive material in said second via hole, and said first via hole connected therewith;
- and
- 7) removing said first and second sacrificial layer.
A method of fabricating a pair of chip connectors for a semiconductor device, comprising:
- a) depositing a first sacrificial layer on said semiconductor device;
- b) etching a first via hole in said first sacrificial layer;
- c) plating a first conductive material in said first via hole;
- d) depositing a second sacrificial layer on said first sacrificial layer;
- e) etching a second via hole in said second sacrificial layer and said first sacrificial layer;
- f) plating a second conductive material in said second via hole;
- and
- g) removing said first and second sacrificial layer.
Dependencies are inferred from the claim text.