Hierarchical access of test access ports in embedded core integrated circuits
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
An integrated circuit can have plural core circuits, each having a test access ports that is defined in IEEE Standar 1149.1. Access to and control of these ports is though a test linking moduled. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emudulation.
Claims11
An integrated circuit comprising:
- A. plural embedded cores formed in the integrated circuit;
- B. a test access port associated with and connected to each core;
- C. one IC test access port on the integrated circuit, including one test data input lead, one test data output lead, one test clock lead and one test mode select lead;
- D. a linking module connected between the one IC test access port and the core test access ports;
- E. a select output lead from one of the cores that passes through the linking module as an external core output;
- F. an external core enable lead that connects to the linking module;
- G. a gate in the linking module receiving the external core enable lead and producing an enable signal to the one core.
An integrated circuit comprising:
- A. plural core circuits formed in the integrated circuit, each core circuit including a test access port;
- B. a test access port for the integrated circuit;
- C. a firts test linking module coupled between the test access port for the integrated circuit and a first group of the test access port for the core circuits, the first group of the test access ports being less than all of the test access ports for the core circuits;
- and
- D. a second test linking module coupled between the test access port of one core circuit in the first group of the test access ports and a second group of the test access ports for the core circuits.
Dependencies are inferred from the claim text.