Context switching technique for processors with large register files

A method for operating a processor having a plurality of registers holding data, each of the plurality of registers having one or more register information bits associated with it, and a memory, the method comprising the steps of:

• providing a first register save area in the memory, the first register save area holding data values that define a first context;
• providing a second register save area in the memory, the second register save area holding data values that define a second context;
• providing the first context in the processor by loading at least some of the data values from the first register save area into the plurality of registers and by maintaining the one or more register information bits associated with each of the plurality of registers;
• storing a first pointer value which points to the first register save area in a current RFSA register;
• indicating a context switch by storing a second pointer to the second register save area in the current RFSA register;
• transferring the first pointer from the current RFSA register to a previous RFSA register;
• transferring substantially all of the data values that define the first context from the registers to a shadow register file;
• and
• providing the second context in the processor by loading selected data values from the second register file save area into the plurality of registers and by maintaining the one or more register information bits associated with each of the plurality of registers.

A computer program product for use with a general purpose computer, said computer program product comprising:

• a computer usable medium having computer readable program code means embodied in said medium for operating a processor having a plurality of registers holding data and a memory, the computer program product having:
• computer readable program code devices for causing a computer to provide a first register save area in the memory, the first register save area holding data values that define a first context;
• computer readable program code devices for causing a computer to provide a second register save area in the memory, the second register save area holding data values that define a second context;
• computer readable program code devices for causing a computer to provide the first context in the processor by loading at least some of the data values from the first register save area into the plurality of registers;
• computer readable program code devices for causing a computer to store a first pointer value to the first register save area in a current RFSA register;
• computer readable program code devices for causing a computer to indicate a context switch by storing a second pointer to the second register save area in the current RFSA register;
• computer readable program code devices for causing a computer to transfer the first pointer from the current RFSA register to a previous RFSA register;
• computer readable program code devices for causing a computer to transfer all of the data values that define the first context from the registers to a shadow register file;
• and
• computer readable program code devices for causing a computer to provide the second context in the processor by loading selected data values from the second register file save area into the plurality of registers.

A computer system including a processor and a memory, the computer system comprising:

• a general register file including a plurality of general registers holding data;
• an execution unit within the processor operable to access data from selected general registers;
• a first register save area located at an address in the memory, the first register save area storing data held in the plurality of registers;
• a current register file save area (RFSA) register holding a value pointing to the location of the first register save area in memory;
• a shadow register file coupled to receive data from the general register file and to send data to the memory, the shadow register file having an entry for each of the general registers;
• a second register save area located at an address in the memory, the second register save area storing data held in the shadow register file;
• a previous register file save area (RFSA) register coupled to the current register file save area register and holding a value pointing to the location of the second register save area in memory;
• and
• a control connection between the shadow register file, the current RFSA register and the previous RFSA register, wherein the shadow register file is further coupled to send data to the plurality of registers in response to detecting that the current RFSA value equals the previous RFSA value.

A method for operating a processor having a plurality of registers holding data and a memory, the method comprising the steps of:

• providing a first register save area in the memory, the first register save area holding data values that define a first context;
• providing a second register save area in the memory, the second register save area holding data values that define a second context;
• providing the first context in the processor by loading at least some of the data values from the first register save area into the plurality of registers;
• storing a first pointer value which points to the first register save area in a current RFSA register;
• indicating a context switch by storing a second pointer to the second register save area in the current RFSA register;
• transferring the first pointer from the current RFSA register to a previous RFSA register;
• transferring substantially all of the data values that define the first context from the registers to a shadow register file;
• and
• providing the second context in the processor by loading selected data values from the second register file save area into the plurality of registers on a register by register basis as needed by a thread executed on the processor.

A method for operating a processor having a plurality of registers holding data and a memory, the method comprising the steps of:

• providing a first register save area in the memory, the first register save area holding data values that define a first context;
• providing a second register save area in the memory, the second register save area holding data values that define a second context;
• providing the first context in the processor by loading at least some of the data values from the first register save area into the plurality of registers;
• storing a first pointer value which points to the first register save area in a current RFSA register;
• indicating a context switch by storing a second pointer to the second register save area in the current RFSA register;
• transferring the first pointer from the current RFSA register to a previous RFSA register;
• transferring substantially all of the data values that define the first context from the registers to a shadow register file;
• and
• providing the second context in the processor by:
• (1) loading selected data values from the second register file save area into the plurality of registers;
• (2) marking each of the plurality of registers with a valid bit indicating whether the data of the register is effective data;
• (3) setting each of the valid bits to indicate that the data is not effective data;
• (4) each time a register is accessed, retrieving data from the accessed register if the valid bit indicates that the data is effective;
• and (5) each time a register is accessed, retrieving data from the register file save area if the valid bit indicates that the data is not effective, filling the register with the retrieved data, and setting the valid bit for the register to indicate that the register's data is now effective.