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AssigneeQUALCOMM Incorporated
InventorsSeyfollah Bazarjani, Sean Wang, Vincenzo Peluso
Estimating the term…
A control mechanism that can be used to control a ΣΔ ADC to provide the required level of performance while reducing power consumption. The ΣΔ ADC is designed with multiple stages (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a ΣΔ ADC that is similar to the ΣΔ ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditioned samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more ΣΔ stages in the ΣΔ ADC.
A data conversion circuit comprising:
A method for controlling ΣΔ stages in a sigma-delta analog-to-digital converter (ΣΔ ADC) comprising:
An electronic circuit comprising:
A control circuit for controlling a multi-stage circuit that includes a plurality of signal stages, the control circuit comprising:
Dependencies are inferred from the claim text.