Defect management for interface to electrically-erasable programmable read-only memory

A method to interface a host processor to an electrically-erasable memory in a memory space, the memory space defining a plurality of segments and each of the segments including a plurality of sectors, including:

• regulating access by the host processor to the electrically-erasable memory in the memory space;
• reading at least one sector valid indication from a segment of the media;
• determining a non-defective sector from the at least one sector valid indication read;
• reading a sector-level segment defect map from the sector determined to be non-defective;
• determining, from the sector-level segment defect map read, sectors within the segment that are valid;
• wherein the step of regulating access operates at least in part on the determinations in the sector defect determination step.

A method for tracking defective segments of an electrically-erasable read-only memory in a memory space, the memory space defining a plurality of segments, including:

• reading a manufacture defect list, the manufacture defect list being an indication of one or more first segments that cannot be written during a low-level format of the memory;
• creating a hard defect table from the manufacture defect list to indicate the first segments of the memory are unusable;
• attempting to erase a second segment of the memory and determining whether the erasure is a failure;
• modifying the hard defect table to also indicate one or more second segments of the memory, that are not one of the first segments, is unusable based on the determination that the erasure of the second segment is a failure,
• wherein access to the memory is based at least in part on the hard defect table.

A system that tracks defective segments of an electrically-erasable read-only memory in a memory space, the memory space defining a plurality of segments, including:

• means for reading a manufacture defect list, the manufacture defect list being an indication of one or more first segments that cannot be written during a low-level format of the memory;
• means for creating a hard defect table from the manufacture defect list to indicate the first segments of the memory are unusable;
• means for attempting to erase a second segment of the memory and determining whether the erasure is a failure;
• means for modifying the hard defect table to also indicate one or more second segments of the memory, that are not one of the first segments, is unusable based on the determination that the erasure of the second segment is a failure,
• wherein access to the memory is based at least in part on the hard defect table.

A memory system for use by a host processor, including:

• electrically erasable memory addressable by the host processor in the memory space of the host processor, the memory space defining a plurality of segments and each of the segments including a plurality of sectors;
• media interface means that regulates access by the host processor to the electrically-erasable memory in the memory space;
• sector valid indication reading means to read at least one sector valid indication from a segment of the media;
• sector valid determination means to determine a non-defective sector from the at least one sector valid indication read;
• sector level segment defect map indication reading means to read a sector-level segment defect map from the sector determined to be non-defective;
• sector defect determination means to determine, from the sector-level segment defect map read, sectors within the segment that are valid;
• access regulation means to regulate access to the memory space at least in part on the determinations by the sector defect determination means.