Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence

A random access memory module which provides a burst sequence of data in response to a request packet, wherein the burst sequence of data includes a plurality of data blocks and wherein the request packet includes on or more data ordering bits which define a data ordering, the random access memory module comprising:

• a memory array having a plurality of memory cells organized in an array of rows and columns;
• a row address decoder connected to the memory array, wherein the row address decoder generates a row address which addresses one of the rows of the memory array;
• and
• a column address decoder connected to the memory array, wherein the column address decoder generates a column address which addresses one of the columns of the memory array, wherein the column address decoder includes data ordering control logic for placing data blocks retrieved from the memory array within the burst sequence as a function of the data ordering bits in the request packet such that consecutive burst sequences can be transferred in different data orderings, the data ordering control logic having a sequencer which generates bits of the column address used to achieve the desired data ordering and a first incrementer which generates the most significant bits of the column address.

A memory system which provides a plurality of data words in response to a read request, wherein the read request includes an address, the memory system comprising:

• a controller, wherein the controller generates a request packet in response to the read request and wherein the request packet includes one or more data ordering bits which define a data ordering;
• a synchronous random access memory;
• a collector;
• and
• a synchronous memory bus connected to the controller, the random access memory and the collector;
• wherein the controller transfers the request packet over the synchronous memory bus to the random access memory on receipt of a read request;
• wherein the synchronous random access memory provides a burst sequence of data over the synchronous memory bus to the collector in the data ordering defined in the request packet;
• and
• wherein the collector receives the burst sequence of data from the random access memory and forms the burst sequence of data into the plurality of data words.

A computer system, comprising:

• an address bus;
• a data bus;
• a processor connected to the address bus and the data bus, wherein the processor issues read requests, wherein the read requests include address information;
• a cache connected to the address bus and the data bus, wherein the cache includes cache memory, wherein the cache stores cache lines in said cache memory and wherein the cache attempts to fill read requests from the cache lines stored in the cache memory;
• and
• a memory module connected to the address bus and the data bus, wherein the memory module includes:
• a controller, wherein the controller generates a request packet in response to the read request when the cache cannot fill the read request from the cache lines stored in the cache memory, wherein the request packet includes the address information and one or more data ordering bits which define a data ordering;
• a synchronous random access memory,
• a collector;
• and
• a synchronous memory bus connected to the controller, the random access memory and the collector;
• wherein the controller transfers the request packet over the synchronous memory bus to the random access memory;
• wherein the synchronous random access memory provides a burst sequence of data over the synchronous memory bus to the collector in the data ordering defined in the request packet;
• wherein the collector receives the burst sequence of data from the random access memory and forms the burst sequence of data into the plurality of data words;
• and
• wherein the plurality of data words replace one of the cache lines stored in the cache memory.

A method of transferring data between a packet-oriented synchronous memory device and a processor, wherein the synchronous memory device includes a column address controller, wherein the column address controller includes a sequencer which controls one or more bits of a column address, the method comprising the steps of:

• assembling a plurality of request packets, including setting bits in the request packets as a function of memory bus width, wherein each request packet controls a particular burst sequence and wherein each request packet includes one ore more data ordering bits which define a data ordering for the particular burst sequence;
• transferring one of the plurality of request packets to the synchronous memory device;
• controlling the sequence as a function of the data ordering bits transferred in the transferred request packet;
• and
• transferring the data to the processor in the data ordering defined for the burst sequence controlled by the transferred request packet.

A method of transferring data between a packet-oriented synchronous memory device and a processor, wherein the synchronous memory device includes a column address controller, wherein the column address controller includes a sequencer which controls one or more bits of a column address, the method comprising the steps of:

• assembling a plurality of request packets, including setting bits in the request packets as a function of burst length, wherein each request packet controls a particular burst sequence and wherein each request packet includes one ore more data ordering bits which define a data ordering for the particular burst sequence;
• transferring one of the plurality of request packets to the synchronous memory device;
• controlling the sequence as a function of the data ordering bits transferred in the transferred request packet;
• and
• transferring the data to the processor in the data ordering defined for the burst sequence controlled by the transferred request packet.