Chip capacitance measurement circuit

A chip capacitance measurement circuit, comprising:

• a measurement circuit;
• a power supply;
• a first current meter connected between the measurement circuit and the power supply;
• a second current meter connected between the measurement circuit and the power supply;
• and
• a signal generator coupled with the measurement circuit to control a current flowing there through;
• wherein the first current meter and the second current meter measure the currents flowing from the power supply to the measurement circuit, the signal generator controls a switch of the measurement circuit, and the measurement circuit, having a first wire capacitor, a second wire capacitor, and a to-be-measured capacitor, further includes:
• a first pair of matching PMOS transistors that includes a first PMOS transistor and a second PMOS transistor, wherein the source terminal of the first PMOS transistor is connected to the first current meter, the source terminal of the second PMOS transistor is connected to the second current meter, and the gate terminal of the first PMOS transistor and the gate terminal of the second PMOS transistor are connected to a first output terminal of the signal generator;
• a second pair of matching PMOS transistors that includes a third PMOS transistor and a fourth PMOS transistor, wherein the source terminal of the third PMOS transistor is connected to the drain terminal of the first PMOS transistor, the source terminal of the fourth PMOS transistor is connected to the drain terminal of the second PMOS transistor, and the gate terminal of the third PMOS transistor and the gate terminal of the fourth PMOS transistor are connected to a second output terminal of the signal generator, and
• a third pair of matching NMOS transistors that includes a first NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor and the third PMOS transistor have a common drain terminal connection from which the first wire capacitor connects to a ground, the second NMOS transistor and the fourth PMOS transistor have a common drain connection from which the second wire capacitor and the to-be-measured capacitor connect to the ground, the gate terminal of the first NMOS transistor and the gate terminal of the second NMOS transistor are connected to a third output terminal of the signal generator, and the source terminal of the first NMOS transistor and the source terminal of the second NMOS transistor are connected to the ground;
• whereby negative currents generated by the measurement circuit and returned to the current measuring devices are identical so that an accurate determination of the capacitance of the to-be-measured capacitor is achieved from measuring charging currents delivered via the power supply to the measurement circuit.

A chip capacitance measurement circuit, comprising:

• a power source;
• a plurality of current meters connected to the power source;
• a signal generator;
• and
• a measurement circuit coupled with the signal generator and the current meters, wherein the measurement circuit includes a plurality of component circuits that are coupled with one another and connected to the signal generator, the component circuits being replicated from a basic circuit structure that is comprised of at least two PMOS transistors and a NMOS transistor having their respective drain and source terminals connected to one another from the current meters to a ground, wherein one of the component circuits further includes a to-be-measured capacitor, whereby the capacitance of the to-be-measured capacitor is determined from a current flowing through the measurement circuit that is controlled via the signal generator.