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US 6,401,167 B1Granted
High performance cost optimized memory
AssigneeRambus Inc.
InventorsRichard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
Life of this patent
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Abstract
A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.
Claims67
A memory device comprising:
- a memory core;
- a first interface to couple to a first external signal path;
- a second interface to couple to a second external signal path distinct from the first external signal path;
- and
- circuitry coupled to the memory core and coupled to the first and second interfaces to receive first and second types of memory control packets respectively therefrom, the circuitry being configured to access a memory cell within the memory core in response to address information and command information provided within the first type of memory control packet and address information and control information provided within the second type of memory control packet.
2 more elements
A memory controller comprising:
- a first interface to couple to a first external signal path;
- a second interface to couple to a second external signal path distinct from the first external signal path;
- and
- circuitry to output a first type of memory control packet via the first interface and a second type of memory control packet via the second interface, the first and second types of memory control packets both including both address information and command information for accessing memory cells within a memory device coupled to the first and second external signal paths;
- wherein the address information and command information for accessing a specified memory cell is provided in part by the address and command information in the first type of memory control packet and in part by the address and command information in the second type of memory control packet.
2 more elements
A memory system, comprising:
- a first signal path;
- a second signal path distinct from the first external signal path;
- a first memory device coupled to the first and second signal paths and including a plurality of memory cells;
- and
- a memory controller coupled to the first and second signal paths to output a first type of memory control packet to the first memory device on the first signal path and to output a second type of memory control packet to the first memory device on the second signal path, the first and second types of memory control packets both including both address information and command information for accessing the plurality of memory cells within the first memory device;
- wherein the address information and command information for accessing a specified memory cell is provided in part by the address and command information in the first type of memory control packet and in part by the address and command information in the second type of memory control packet.
3 more elements
Dependencies are inferred from the claim text.