Loopback direct memory access control system for a digital scanner
AssigneeXerox Corporation
InventorsGordon F. Lupien, Jr., Robert M. Chapin, Anthony M. Frumusa
Life of this patent
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Abstract
The present invention generally relates to a loopback direct memory access control system for a digital scanner for processing images. More specifically, the present invention is directed to a method and apparatus for quickly reading digital data from memory, processing the digital data and writing the processed digital data to memory.
Claims22
A direct memory access controller, coupled to an image processing unit, a data compression unit and FIFO, for storing digital data in a memory and retrieving digital data from memory, comprising:
- a compression and decompression bus control logic unit;
- a bypass interface;
- a data selector;
- a computing unit instructing the data selector to select the routing of digital data by way of the bypass interface or by way of the FIFO controlled by the compression and decompression bus control logic unit;
- a data packer receiving the selected digital data from the data selector and packing the digital data into words;
- a write DMA master receives the words of digital data from the data packer and places the words into blocks of digital data and stores the blocks of digital data in the memory;
- a read DMA master retrieves blocks of digital data from memory;
- a bus control logic reading digital data from the read DMA master and writing the digital data to the image processing unit, wherein the image processing unit outputs the processed digital data to one of the FIFO, ITU G3/G4 and JPEG as directed by the computing unit and the processed digital data is subsequently routed as directed by the computing unit and subsequently stored in the memory by the write DMA master.
A direct memory access method for reading digital data from memory and writing digital data to memory comprising:
- (a) initializing DMA controller having a read DMA master and a write DMA master;
- (b) writing digital data from the memory to the read DMA master internal FIFO;
- (c) reading digital data from the read DMA master internal FIFO and writing the digital data to the image processing unit under the control of the bus control logic;
- (d) processing the digital data to provide processed digital data to the data packer;
- (e) writing words of digital data from data packer to write DMA master internal FIFO for front block;
- (f) writing digital data to memory starting at the front block address in bursts until the transfer of digital data for the front block is completed;
- (g) loading write DMA master back block address and size into front block and next block address and size into write DMA master front block;
- and
- (h) repeating steps (b) and (c) while performing step (d) and steps (e) through (g) until the transfer of digital data is complete.
A direct memory access method for reading digital data from memory and writing digital data to memory comprising:
- (a) initializing image processing unit and data compression unit;
- (b) selecting path of digital data in DMA controller;
- (c) setting width of words of digital data in data packer;
- (d) initializing write DMA master front block and back block addresses and sizes and read DMA master front block and back block addresses and sizes;
- (e) setting threshold and burst size of write DMA master internal FIFO and read DMA master internal FIFO;
- (f) enabling write DMA master and read DMA master;
- (g) writing digital data from the memory to the read DMA master internal FIFO;
- (h) reading digital data from the read DMA master internal FIFO and writing the digital data to the image processing unit under the control of the bus control logic;
- (i) processing the digital data to provide processed digital data to the data packer;
- (j) writing words of digital data from data packer to write DMA master internal FIFO for front block;
- (k) writing digital data to memory starting at the front block address in bursts until the transfer of digital data for the front block is completed;
- (l) loading write DMA master back block address and size into front block and next block address and size into write DMA master front block;
- and
- (m) repeating steps (g) and (h) while performing step (i) and steps (j) through (k) until the transfer of digital data is complete.
Dependencies are inferred from the claim text.