Semiconductor memory device and method of checking same for defect
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsHideto Hidaka, Mikio Asakura, Kiyohiro Furutani, Tetsuo Kato
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Abstract
A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
Claims6
A semiconductor memory device comprising:
- normal memory cells;
- a decoder for simultaneously selecting a plurality of normal memory cells among said normal cells and at least one spare memory cell among said spare memory cells;
- and
- test circuit for producing a result of detecting whether data read from said plurality of normal memory cells match or not, and producing test data corresponding to data read from said at least one spare memory cell.
Dependencies are inferred from the claim text.