Logic circuit and its forming method
AssigneeHitachi, Ltd.
InventorsShunzo Yamashita, Kazuo Yano, Yasuhiko Sasaki
Life of this patent
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Abstract
This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).
Claims5
A method for designing a logic circuit including a plurality of logic gates having terminals by using a computer, comprising the steps of:
- calculating slack values of each of the input terminals of each of the logic gates;
- calculating a smallest difference value between the slack values of the input terminals of each of the logic gates and specifying a first logic gate and a second logic gate whose smallest difference value is smaller than that of the first logic gate;
- and
- converting a part of the logic circuit including the first logic gate so as to satisfy an object delay time tolerance.
Dependencies are inferred from the claim text.