Apparatus and method for generating a distributed clock signal using gear ratio techniques

An apparatus for transferring data with minimum latency between a first clock domain, a second clock domain and a third clock domain, said apparatus comprising:

• a first clock generator configured to generate a first dependent output clock;
• a second clock generator configured to generate a second dependent output clock;
• a main clock source configured to generate a reference clock for said first and second clock generators;
• gear ratio logic circuitry configured to receive said reference clock and said first and second dependent output clocks,
• said gear ratio logic circuitry configured to generate a first gear ratio output clock from said reference clock, said first gear ratio output clock having a frequency being a first fraction, J/M, of the frequency of said reference clock, where J and M are integers,
• said first and second clock generators receiving said first gear ratio output clock as a reference-phase clock, said gear ratio logic circuitry configured to generate a second gear ratio output clock from said first dependent output clock,
• said second gear ratio output clock having a frequency being a second fraction, K/N1, of the frequency of said first dependent output clock, where K and N1 are integers, said first clock generator receiving said second gear ratio output clock as a dependent-phase clock,
• said gear ratio logic circuitry further configured to generate a third gear ratio output clock from said second dependent output clock, said third gear ratio output clock having a frequency being a third fraction, L/N2, of the frequency of said second dependent output clock, where L and N2 are integers, said second clock generator receiving said third gear ratio output clock as a dependent-phase clock,
• said first clock generator including phase alignment circuitry to phase shift said first dependent output clock such that a detected phase difference between said first and second gear ratio output clocks is substantially zero, and said second clock generator including phase alignment circuitry to phase shift said second dependent output clock such that a detected phase difference between said first and third gear ratio output clocks is substantially zero;
• first circuitry operating in said first clock domain in response to said reference clock, wherein said gear ratio logic circuitry is configured to generate a first transfer enable signal based on said reference and first dependent output clocks, said first circuitry configured to receive said first transfer enable signal;
• second circuitry operating in said second clock domain in response to said first dependent output clock, wherein said gear ratio logic circuitry is configured to generate a second transfer enable signal based on said reference and second dependent output clocks, said second circuitry configured to receive said second transfer enable signal;
• and
• third circuitry operating in said third clock domain in response to said second dependent output clock.

An apparatus to receive a reference clock and a dependent clock for transferring data between a first clock domain and a second clock domain, said apparatus, comprising:

• first circuitry configured to operate in the first clock domain in response to said reference clock;
• second circuitry configured to operate in the second clock domain in response to a dependent clock, said dependent clock having a frequency substantially equal to an integer ratio of a frequency of said reference clock and having a determined phase relationship with said reference clock;
• and
• gear ratio logic circuitry coupled to said first circuit and said second circuit, said gear ratio logic circuitry configured to receive said reference and dependent clocks and to generate a transfer enable signal based on said reference and dependent clocks, wherein said first circuitry is configured to receive said transfer enable signal and said transfer enable signal permits synchronous, minimum latency information transfers between said first circuitry and said second circuitry.