PLL detection circuit with lock judgement circuit
AssigneeSony Corporation
InventorsNorihiro Murayama, Kosuke Fujita
Life of this patent
Estimating the term…
Abstract
Phase locked loop (PLL) detection circuit that can improve the stability of operation, avoid occurrence of an erroneous operation, and perform PLL lock judgment correctly. Whether a PLL circuit that consists of a phase comparator, a low-pass filter, and a VCO is in a lock state is judged based on a phase error signal in the PLL circuit. The level of the phase error signal is compared with two threshold values, VRL and VRH. When the phase error signal is somewhere between VRL and VRH, a judgment is made that the PLL circuit is in a lock state. A judgment that the PLL circuit is out of a lock state is made in the other cases. This makes it possible to output a correct and stable PLL lock judgment signal.
Claims12
A PLL detection circuit comprising:
- a PLL circuit including a phase comparison circuit for performing a comparison of phases of an input signal and an oscillation signal and outputting a phase error signal corresponding to a phase error between the input signal and the oscillation signal based on a result of the comparison and an oscillation circuit for generating the oscillation signal and for controlling an oscillation frequency of the oscillation signal in accordance with the phase error signal;
- a PLL lock judgment circuit for judging whether the PLL circuit is in a lock state based on the phase error signal so as to judge that the PLL circuit is in a lock state when a voltage level of the phase error signal is in a prescribed range and to judge that the PLL circuit is out of a lock state when the voltage level of the phase error signal is out of the prescribed range;
- and
- a selection circuit for selecting a first signal corresponding to the phase error signal or a second signal having a prescribed voltage level in accordance with a judgment result of the PLL lock judgment circuit and outputting the selected signal as an automatic fine tuning control-signal.
A PLL detection circuit comprising:
- an AGC amplification circuit for amplifying an input signal at a prescribed gain;
- a PLL circuit including a phase comparison circuit for comparing a phase of an output signal of the AGC amplification circuit and a phase of an oscillation signal generated by an oscillation circuit and outputting a phase error signal corresponding to a phase error between the input signal and the oscillation signal based on a result of the comparison of the phase comparison circuit, wherein the oscillation circuit generates the oscillation signal while controlling an oscillation frequency thereof in accordance with the phase error signal;
- a PLL lock judgment circuit for judging whether the PLL circuit is in a lock state based on the phase error signal by judging that the PLL circuit is in a lock state when a voltage level of the phase error signal is in a prescribed range and judging that the PLL circuit is out of the lock state when the voltage level of the phase error signal is out of the prescribed range;
- a detection circuit for detecting the output signal of the AGC amplification circuit by using the oscillation signal as a reference signal and outputting a detection signal;
- a first loop filter for extracting a prescribed frequency component from a signal that is based on the detection signal;
- a selection circuit for selecting one of a first signal output from the first loop filter and a second signal in accordance with a judgment result of the PLL lock judgment circuit and outputting the selected signal;
- and
- an AGC control circuit for generating, in accordance with the selected signal of the selection circuit, a gain control signal for controlling a gain of the AGC amplification circuit and supplying the gain control signal to the AGC amplification circuit.
Dependencies are inferred from the claim text.