US 6,396,316 B1 · Clock buffer with LC circuit for jitter reduction

Abstract

A clock buffer circuit utilizing an LC circuit for jitter reduction. The circuit includes a differential amplifier that is coupled to a buffer stage. The output of the buffer circuit comprises the buffer stage output. An inductor and capacitor are coupled between the buffer stage output and ground. The values of the inductor and capacitor are specified such that the resonant frequency of the LC circuit corresponds to the nominal clock frequency. The entire buffer circuit including the capacitor and inductor may be fabricated on an integrated circuit. Alternatively the capacitor and/or inductor may comprise discrete components that are coupled to the buffer stage output. Additionally, multiple capacitors and/or inductors may be fabricated on the integrated circuit to permit the resonant frequency of the LC circuit to be adjusted to match the nominal clock frequency. The capacitor(s) and/or inductor(s) on the integrated circuit may be connected to integrated circuit contacts and coupled to the buffer stage output via external connections or alternatively, via semiconductor switches.

Claims16

Dependent claims

A buffer circuit for reducing clock jitter comprising:

a buffer having at least one input for receiving at least one input clock signal having a nominal clock frequency and further having a buffer output, said buffer being operative to provide an output clock signal at said buffer output responsive to the receipt of said at least one input clock signal;
at least one inductive element having an inductance value, said at least one inductive element being coupled between said buffer output and a first low impedance node of said buffer circuit;
and
at least one capacitive element having a capacitance value, said at least one capacitive element being coupled between said buffer output and a second low impedance node of said buffer circuit;
said at least one inductive element and said at least one capacitive element having a resonant frequency and said inductance value and said capacitance value being specified such that said resonant frequency corresponds to said nominal clock frequency;
wherein said buffer includes an amplifier stage having an output coupled to an input of a first buffer stage, said at least one input of said buffer comprises at least one input to said amplifier stage and said buffer output comprises an output of said first buffer stage.

3 more elements

An integrated clock buffer circuit for reducing jitter comprising:

a semiconductor die, said die having fabricated thereon:
a buffer having at least one input for receiving at least one input clock signal having a nominal clock frequency and further having a buffer output, said buffer being operative to provide an output clock signal at said buffer output responsive to the receipt of said at least one input clock signal;
at least one inductive element having an inductance value, said at least one inductive element being coupled between said buffer output and a ground node of said buffer circuit;
and
said at least one capacitive element having a capacitance value, said at least one capacitive element being coupled between said buffer output and said ground node of said buffer circuit;
said at least one inductive element and said at least one capacitive element having a resonant frequency and said inductance value and said capacitance value being specified such that said resonant frequency corresponds to said nominal clock frequency;
wherein at least one capacitive element includes a plurality of capacitive elements and said capacitive elements are selectably coupleable between said buffer output and said ground node.

4 more elements

Dependencies are inferred from the claim text.

Clock buffer with LC circuit for jitter reduction

Life of this patent

Clock buffer with LC circuit for jitter reduction

Life of this patent

Abstract

Claims16