Semiconductor device provided with on-chip decoupling condenser utilizing CMP dummy patterns

Abstract

A dummy pattern for use in a chemical mechanical polishing (CMP) process is disposed in a field dummy region within a p− well region, isolated by an isolating insulating film, wherein the p− well region has a potential fixed by a ground electrode. The dummy pattern includes a gate insulating film dummy pattern and a gate electrode dummy pattern, formed in the same layers as a gate insulating film and a gate electrode, respectively, of an NMOS transistor. The gate electrode dummy pattern is connected with a contact plug, which in turn is connected with a power supply electrode (Vcc) interconnection line. Thus, a decoupling condenser, formed of the field dummy region within the p− well, the gate insulating film dummy pattern and the gate electrode dummy pattern by utilizing the dummy patterns for use in the CMP process, is connected in parallel with a primary electronic circuit. As a result, a semiconductor device is obtained which operates at a low voltage with suppressed electromagnetic interference (EMI), without increasing an area occupied by the semiconductor device.

Dependencies are inferred from the claim text.