High-precision biasing circuit for a cascoded CMOS stage, particularly for low noise amplifiers

A biasing circuit for a cascode stage comprising first and second transistors serially connected between a first voltage reference and a second voltage reference, the biasing circuit comprising:

• a first replica transistor matched to the first transistor and connected thereto, the first replica transistor comprising a control terminal and a conduction terminal;
• a second replica transistor matched to the second transistor and connected to the first voltage reference, the second replica transistor comprising a control terminal and a conduction terminal;
• a first current generator for biasing said first replica transistor;
• a second current generator for biasing said second replica transistor;
• and
• a detection circuit for detecting a voltage value on the conduction terminal of said second replica transistor and for applying a voltage to the control terminal of said first replica transistor.

An amplifier comprising:

• a cascode stage comprising first and second transistors serially connected between a first voltage reference and a second voltage reference;
• a biasing circuit connected to said cascode stage and comprising
• a first replica transistor matched to said first transistor and connected thereto, said first replica transistor comprising a control terminal and a conduction terminal,
• a second replica transistor matched to said second transistor and connected to the first voltage reference, said second replica transistor comprising a control terminal and a conduction terminal,
• a first current generator for biasing said first replica transistor,
• a second current generator for biasing said second replica transistor, and
• a detection circuit for detecting a voltage value on the conduction terminal of said second replica transistor and for applying a voltage to the control terminal of said first replica transistor.

A method for biasing a cascode stage comprising first and second transistors serially connected between a first voltage reference and a second voltage reference, the method comprising:

• biasing a first replica transistor matched to the first transistor and connected thereto, the first replica transistor comprising a control terminal and a conduction terminal;
• biasing a second replica transistor matched to the second transistor and connected to the first voltage reference, the second replica transistor comprising a control terminal and a conduction terminal;
• detecting a signal on the conduction terminal of the second replica transistor;
• and
• applying a predetermined bias to the control terminal of the first replica transistor based upon the detected signal.