Process for forming gate conductors
AssigneeAdvanced Micro Devices, Inc.
InventorBin Yu
Life of this patent
Estimating the term…
Abstract
An ultra-large-scale integrated (ULSI) circuit includes MOSFETs. The MOSFETs can include a gate structure manufactured by utilizing a spacer structure as a mask. The spacer structure can be silicon dioxide formed in an etch back process.
Claims20
A method of manufacturing an integrated circuit including a plurality of transistors, the plurality of transistors including a first transistor having a gate structure disposed on a film, the method comprising:
- removing portions of a mask layer above a conductive layer above the film to form a mask feature, the mask feature having at least one sidewall;
- providing an oxide material above the mask, the oxide material being a thick, non-conformal layer;
- removing portions of the oxide material above the mask feature and the conductive layer to leave a spacer on the at least one sidewall;
- removing the mask feature;
- and
- etching the conductive layer in accordance with the spacer, thereby forming the gate structure.
A process of forming a gate conductor having a dimension less than one lithographic feature, the process comprising:
- providing a conductive layer above a top surface of a substrate;
- providing a mask layer above the conductive layer, the mask layer having a first thickness;
- patterning the mask layer to have a sidewall;
- providing a non-conformal insulative material above the mask layer, the insulative material having a second thickness greater than the first thickness;
- forming an insulative spacer from the insulative material on the sidewall of the mask layer;
- removing the mask layer;
- and
- etching the conductive layer in accordance with the insulative spacer as a mask to form the gate conductor.
A method of manufacturing a plurality of gate structures on an ultra-large scale integrated circuit, the gate structures having at least one dimension less than 50 nm, the method comprising steps of:
- depositing a mask layer over a top surface of a conductive layer above a substrate;
- lithographically patterning the mask layer to have a plurality of islands, the islands having a minimum topographic dimension at least 50 nm wide;
- providing a non-conformal spacer layer above the islands, the spacer layer at least completely filling the gaps between the islands;
- forming spacers on sidewalls of the islands from the spacer layer;
- removing the islands;
- and
- removing portions of the conductive layer in accordance with the spacers, the spacers being a hard mask for the removing portions step.
Dependencies are inferred from the claim text.