US 6,389,580 B1 · Computer readable storage medium having logic synthesis program, and logic synthesis method and apparatus

Abstract

A computer readable storage medium has a logic synthesis code embodied therein. The logic synthesis code includes a standard design function for causing a computer to generate standard circuit information about target circuitry on which a logic synthesis function is to be performed, based on specifications of the target circuitry written in a hardware description language, the standard circuit information logically matching the specifications; a timing design function for causing the computer to generate modified circuit information by modifying the standard circuit information so that the standard circuit information satisfies both an ideal clock signal condition defining an ideal clock signal to be applied to one or more sequential circuits included in target circuitry, and at least either of a first ideal assertion period condition defining an ideal period of time during which each of one or more tristate buffers included in the target circuitry is asserted and a second ideal assertion period condition defining an ideal period of time during which each of one or more other sequential circuits for latching an output of a tristate buffer, which are included in the target circuitry is asserted; and an output function for outputting the modified circuit information from the timing design function.

Claims20

Dependent claims

A computer readable storage medium having logic synthesis code means embodied therein, said logic synthesis code means comprising:

standard design means for causing a computer to generate standard circuit information about target circuitry on which a logic synthesis function is to be performed, based on specifications of the target circuitry written in a hardware description language, said standard circuit information logically matching said specifications;
timing design means for causing the computer to generate modified circuit information by modifying said standard circuit information so that said standard circuit information satisfies both an ideal clock signal condition defining an ideal clock signal to be applied to one or more sequential circuits included in said target circuitry, and at least either of a first ideal assertion period condition defining an ideal period of time during which each of one or more tristate buffers included in said target circuitry is asserted and a second ideal assertion period condition defining an ideal period of time during which each of one or more other sequential circuits for latching an output of a tristate buffer, which are included in said target circuitry is asserted;
and
output means for outputting said modified circuit information from said timing design means.

1 more element

A computer-implemented logic synthesis method for generating information about a constitution of target circuitry on which a logic synthesis function is to be performed based on specifications of the target circuitry written in a hardware description language, said method comprising the steps of:

generating standard circuit information about the target circuitry based on the specifications of said target circuitry, said standard circuit information logically matching said specifications;
and
modifying said standard circuit information so that said standard circuit information satisfies both an ideal clock signal condition defining an ideal clock signal to be applied to one or more sequential circuits included in said target circuitry, and at least either of a first ideal assertion period condition defining an ideal period of time during which each of one or more tristate buffers included in said target circuitry is asserted and a second ideal assertion period condition defining an ideal period of time during which each of one or more sequential circuits each for latching an output of a tristate buffer, which are included in said target circuitry is asserted.

A logic synthesis apparatus for generating information about a constitution of target circuitry based on specifications of the target circuitry written in a hardware description language, comprising:

storage means for storing said specifications of the target circuitry, an ideal clock signal condition defining an ideal clock signal to be applied to one or more sequential circuits included in said target circuitry, and at least either of a first ideal assertion period condition defining an ideal period of time during which each of one or more tristate buffers included in said target circuitry is asserted and a second ideal assertion period condition defining an ideal period of time during which each of one or more other sequential circuits each for latching an output of a tristate buffer, which are included in said target circuitry is asserted;
standard design means for generating standard circuit information about said target circuitry based on said specifications stored in said storage means, said standard circuit information logically matching said specifications;
timing design means for generating modified circuit information by modifying said standard circuit information so that said standard circuit information satisfies both said ideal clock signal condition and at least either of said first and second ideal assertion period conditions;
and
output means for outputting said modified circuit information.

2 more elements

Dependencies are inferred from the claim text.

Computer readable storage medium having logic synthesis program, and logic synthesis method and apparatus

Life of this patent

Computer readable storage medium having logic synthesis program, and logic synthesis method and apparatus

Life of this patent

Abstract

Claims20