Analyzing CMOS circuit delay

A method for providing a timing rule database for an integrated circuit design, said method comprising:

• assembling all logically valid paths for said integrated circuit design;
• assembling all input signal specifications for said integrated circuit design, said input signal specifications including rise and fall times of input signals;
• providing a circuit simulator process for simulating said integrated circuit design;
• applying said input signal specifications to said circuit simulator process, said circuit simulator process being effective for simulating iterative applications of input signals from said input signal specifications to said logically valid paths to provide said timing rule database;
• and
• assembling all output load conditions for each node in said integrated circuit design, said output load conditions including minimum and maximum load conditions for each node, said circuit simulator process being effective for simulating said output load conditions in providing said timing rule database.