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US 6,389,566 B1Granted
Edge-triggered scan flip-flop and one-pass scan synthesis methodology
AssigneeS3 Incorporated
InventorsKenneth D. Wagner, Srinivasan R. Iyengar, Mehran Amerian
Life of this patent
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Abstract
An improved scan flip-flop and method of using same. The scan flip-flop has a separate dedicated scan output driven by a scan output signal driver. Scan shift race conditions are minimized by providing a weak scan output signal driver and inserting delay elements within a cell for a scan flip-flop in the scan signal path. The use of the improved scan flip-flop allows for a one-pass scan synthesis process which provides accurate flip-flop cell timing and area information during the design process.
Claims27
A scan flip-flop comprising:
- a data-in signal input, a scan-in signal input, and a test signal input;
- a data-out signal output and a scan-out signal output, the data-out signal output being formed by a data-out signal driver and the scan-out Signal output being formed by a scan-out signal driver, the scan-out signal driver being a weak signal driver;
- and
- the data-out signal output and the scan-out signal output being coupled to the data-in signal input when the test signal input is provided a signal of a first value, and the data-out signal output and the scan-out signal output being coupled to the scan-in signal input when the test signal input is provided a signal of a second valve.
1 more element
A scan flip-flop comprising;
- a multiplexer with a data input, a scan input, a control input, and a multiplexer output;
- a transfer gate with a transfer gate input, a transfer gate output, and at least one clock control signal input, the transfer gate input being coupled to the multiplexer output;
- a first latch with a first latch input and a first latch output, the first latch input being coupled to the transfer gate output;
- a data out signal driver with a data out signal driver input and a data output, the data out signal driver input being coupled to the first latch output;
- and
- a scan out signal driver with a scan out signal driver input and a scan output, the scan out signal driver input being coupled to the data output, and the scan out signal driver being a weak signal driver.
3 more elements
A scan flip-flop comprising:
- a multiplexer with a data input, a scan input, a control input, and a multiplexer output;
- a transfer gate with a transfer gate input, a transfer gate output, and at least one clock control signal input, the transfer gate input being coupled to the multiplexer output;
- a latch with a latch input and a latch output, the latch input being coupled to the transfer gate output;
- a data out signal driver with a data out signal driver input and a data output, the data out signal driver input being coupled to the latch output;
- a circuit delay element with a circuit delay element input and a circuit delay element output, the circuit delay element input being coupled to the data out signal driver;
- and
- a scan out signal driver with a scan out signal driver input and a scan output, the scan out signal driver being a weak signal driver, the scan out signal driver input being coupled to the circuit delay element output.
4 more elements
A method of creating a digital electronic circuit design with scan flip-flops comprising:
- providing a high level language description representing the digital electronic circuit;
- generating a list including logic components and interconnections between the logic components from the high level language description, the list of logic components including a plurality of flip-flop components;
- mapping the logic components to cells specifying electronic circuit components, including mapping the flip-flop components to at least one scan flip-flop cell, the scan flip-flop cell specifying a flip-flop element having at least two inputs, a data input and a scan input, and at least two outputs, a data output and a scan output, with the data output driven by a data output signal driver and the scan output driven by a scan output signal driver, the scan output signal driver being a weak signal driver, the scan output signal driver receiving a signal from the data output signal driver, and the scan output signal driver presenting a substantially known load to the data output signal driver;
- and
- forming a representation of a scan chain by linking a data output of a first of the plurality of scan flip-flop cells to a scan input of a second of the plurality of scan flip-flop cells.
2 more elements
A method using a computer for designing a digital electronic circuit including scan flip-flops forming a scan chain based on a high level language description describing the functions of the digital electronic circuit comprising:
- generating a list including logic components and interconnections between the logic components from the high level language description, the list of logic components including a plurality of flip-flop components;
- mapping the logic components to cells specifying electronic circuit components, including mapping the flip-flop components to at least one scan flip-flop cell, the scan flip-flop cell specifying a flip-flop element having at least two inputs, a data input and a scan input, and at least two outputs, a data output and a scan output, with the data output driven by a data output signal driver and the scan output driven by a scan output signal driver, the scan output signal driver being a weak signal driver, the scan output signal driver receiving a signal from the data output signal driver, and the scan output signal driver presenting a substantially known load to the data output signal driver;
- and
- forming a representation of a scan chain by linking a data output of a first of the plurality of scan flip-flop cells to a scan input of a second of the plurality of scan flip-flop cells.
1 more element
A scan flip-flop comprising:
- a data-in signal input, a scan-in signal input, and a test signal input;
- a data-out signal output and a scan-out signal output, the data-out signal output being formed by a data-out signal driver and the scan-out signal output being formed by a scan-out signal driver, the scan output signal driver being a weak signal driver;
- the data-out signal output and the scan-out signal output being coupled to the data-in signal input when the test signal input is provided a signal of a first value, and the data-out signal output and the scan-out signal output being coupled by a signal path to the scan-in signal input when the test mode input is provided a signal of a second value, with the signal path having delay elements.
A scan flip-flop comprising:
- a multiplexer with a data input, a scan input, a control input, a circuit delay element, and a multiplexer output, the multiplexer output being linked to the data input when the control input is a first value and the multiplexer output being linked to the circuit delay element, which is linked to the scan input, when the control input is a second value;
- a transfer gate with a transfer gate input, a transfer gate output, and at least one clock control signal input, the transfer gate input being coupled to the multiplexer output;
- a latch with a latch input and a latch output, the latch input being coupled to the transfer gate output;
- a data out signal driver with a data out signal driver input and a data output, the data out signal driver input being coupled to the latch output;
- and
- a scan out signal driver with a scan out signal driver input and a scan output, the scan output signal driver being a weak signal driver, the scan out signal driver input being coupled to the latch output.
3 more elements
Dependencies are inferred from the claim text.