DRAM circuit having a testing unit and its testing method

A method for testing a memory circuit,

• the memory circuit comprising:
• a plurality of word lines;
• a plurality of bit line groups each having two bit lines;
• a memory unit positioned between each of the word lines and one bit line of each of the bit line groups wherein the word line connected to the memory unit is used for initiating the memory unit to input or output a binary data bit through the bit line connected to the memory unit;
• a plurality of writing units, each of the writing units comprising two output ports separately connected to the two bit lines of one bit line group for simultaneously outputting two opposite binary data bits;
• a plurality of testing units, each of the testing units comprising at least two input ports separately connected to an output port of one writing unit and the bit line connected to the output port, and a test circuit for generating a test signal according to the inputs from the two input ports;
• a plurality of bit line switches, each of the bit line switches being connected between one output port of each writing unit and the bit line connected to the output port for controlling the output from the output port to the bit line;
• a plurality of latch units, each of the latch units being connected between two bit lines of one bit line group for maintaining the voltage level of the first bit line according to the binary data bit outputted from the memory unit and outputting an opposite binary data bit to the second bit line of the bit line group when one memory unit outputting a binary data bit through a first bit line of one bit line group connected to the memory unit;
• the method for testing the memory unit comprising:
• initiating the memory unit by using the word line connected to the memory unit;
• using the writing unit connected to the memory unit to write a predetermined binary data bit into the memory unit through one output port of the writing unit connected to the memory unit and the bit line switch and bit line connected between the output port of the writing unit and the memory unit;
• switching off the bit line switch after the predetermined binary data bit is written into the memory unit to disconnect the bit line connected to the output port of the writing unit;
• and
• using the testing unit connected between the output port of the writing unit and the disconnected bit line to test if the binary data bit outputted from the memory unit to the disconnected bit line is the same as the binary data bit outputted from the output port of the writing unit.

A memory circuit comprising:

• a memory unit connected with a word line for initiating the memory unit, and a bit line for inputting or outputting a binary data bit;
• a writing unit having an output port connected to the bit line of the memory unit for writing a binary data bit into the memory unit through the bit line;
• a bit line switch connected between the output port of the writing unit and the bit line of the memory unit for controlling the output from the output port to the bit line;
• a testing unit having two input ports separately connected to the output port of the writing unit and the bit line of the memory unit, and a test circuit for generating a test signal according to the inputs from the two input ports;
• a control circuit for controlling the operations of the memory;
• and
• a latch unit connected to the bit line for maintaining the voltage level of the bit line according to the binary data bit outputted from the memory unit when the memory unit outputting a binary data bit to the bit line;
• wherein when testing the memory unit, the control circuit initiates the memory unit by using the word line connected to the memory unit, uses the writing unit to write a predetermined binary data bit into the memory unit through the bit line switch and bit line, switches off the bit line switch to disconnect the bit line from the output port of the writing unit, and uses the testing unit to test if the binary data bit outputted from the memory unit to the disconnected bit line is the same as the predetermined binary data bit outputted from the output port of the writing unit.