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US 6,389,563 B1Granted
Semiconductor memory test circuit and method for the same
AssigneeHyundai Electronics Industries Co., Ltd.
InventorsJin Keun Oh, Young Hee Kim
Life of this patent
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AssigneeHyundai Electronics Industries Co., Ltd.
InventorsJin Keun Oh, Young Hee Kim
Estimating the term…
A semiconductor memory test circuit and a method for the same to reduce the test time in testing a semiconductor memory. The semiconductor memory test circuit includes: a parallel test circuit for performing a parallel test when inputting a battery backup signal (bbu), a column address signal (cas5), a CAS before RAS signal (cbr), a write enable signal (ew), a power-up bar signal (pwrupb), and a row address signal (ras71)); and a test mode circuit which is controlled by a combination of a parallel test signal (pt) and the battery backup signal (bbu) generated from the parallel test circuit, and generates a test time reduction signal (ttrb), whereby the semiconductor memory test circuit compresses one least significant bit indicating a row address of a device in the case of a 4K refresh operation when the test time reduction signal (ttrb) is enabled, and compresses two least significant bits indicating a row address of a device in the case of an 8K refresh operation when the test time reduction signal (ttrb) is enabled.
A semiconductor memory test circuit comprising:
A semiconductor memory test method comprising the steps of:
A semiconductor memory test method comprising the steps of:
Dependencies are inferred from the claim text.