Embedded logic analyzer for a programmable logic device

A method of compiling a logic analyzer along with an electronic design for a programmable logic device (PLD), said method comprising:

• receiving an electronic design for a programmable logic device (PLD), said electronic design including a plurality of internal signal lines;
• receiving a representation of a logic analyzer to be integrated with said electronic design;
• connecting selected internal signal lines of said electronic design to inputs of said logic analyzer;
• and
• a step of performing the function of compiling said electronic design along with said logic analyzer to produce a compiled design suitable for programming said PLD.

A method of compiling a logic analyzer along with an electronic design for a programmable logic device (PLD), said method comprising:

• receiving an electronic design for a programmable logic device (PLD), said electronic design including a plurality of internal signal lines;
• producing a representation of a logic analyzer to be integrated with said electronic design;
• modifying said electronic design to include said logic analyzer;
• connecting selected internal signal lines of said electronic design to inputs of said logic analyzer;
• and
• compiling said modified electronic design to produce a compiled design for programming said PLD.

A method of retrieving data stored in a logic analyzer integrated within a logic device, said method comprising:

• compiling an electronic design which includes a logic analyzer;
• programming a logic device with said compiled electronic design, said logic analyzer being integrated within said logic device;
• arming said logic analyzer in said logic device such that said logic analyzer is arranged to capture internal signals of said logic device;
• issuing a command to said logic analyzer in said logic device to transfer said captured signals;
• and
• receiving said captured internal signals from said logic analyzer such that said signals may be displayed on a user computer.

A programmable logic device (PLD) comprising:

• user circuitry representing one iteration of an electronic design in a design process to create a final PLD, said user circuitry including interior circuitry that is not directly connected to I/O pins of said PLD;
• logic analyzer circuitry integrated within said PLD such that a portion of said interior circuitry is connected to said logic analyzer circuitry;
• and
• control logic arranged to communicate between said integrated logic analyzer and said pins of said PLD, whereby said integrated logic analyzer is arranged to capture data from said interior circuitry and to communicate said data via said pins.