Pulse run-length measurement for HF data signal by dividing accumulated phase difference between first and second zero-crossings by single-cycle range using multiple cycle range sawtooth waveform

A method of recovering an embedded bit clock in successive transitions of a digitized high frequency signal, comprising the steps of:

• generating a sawtooth waveform having
• a phase from 0 to a predetermined multiple of 2π radians;
• initializing the phase of the sawtooth waveform in a range of between 0 and 2π radians beginning at a first transition of the high frequency signal;
• determining an end of the sawtooth waveform at a second transition of the high frequency signal;
• counting the number of 2π radians in the generated sawtooth waveform between the first and second transitions of the high frequency signal;
• and
• recovering the bit clock in successive transitions of the digitized high frequency signal by dividing the number of 2π radians counted between the first and second transitions by 2π.

A system for accurately measuring a pulse width in a high frequency signal while utilizing a low sampling rate, said system comprising:

• an oscillator which generates a sawtooth clock waveform ranging in phase from zero (0) to a multiple of 2π radians, said oscillator having an accumulator register which accumulates phase increments;
• an interpolator which detects a first transition of the signal at a leading edge of the pulse, and detects a second transition of the signal at a trailing edge of the pulse;
• a phase detector which measures the oscillator phase when the interpolator detects the first transition, and measures a second phase increment when the interpolator detects the second transition;
• means for initiating the accumulator register most significant bits (MSBs) to adjust the measured first phase increment so that it lies in a range between zero (0) and 2π radians;
• means for calculating an accumulated phase difference by subtracting the initialized first phase increment from the measured second phase increment;
• and
• means for dividing the accumulated phase difference by 2π to obtain the pulse width.

An all digital locked loop for recovering a bit clock embedded in a digitized high frequency signal, comprising:

• a phase detector providing a digital output in response to a transition of the digitized high frequency signal;
• a low pass filter providing an output frequency signal in response to the digital output provided by said phase detector;
• a variable oscillator
• generating a sawtooth waveform signal ranging in phase from 0 to a predetermined multiple of 2π radians in response to the output frequency signal from said low pass filter and
• providing a radians number signal representing an accumulation of the number of radians provided to said phase detector at a first transition of the high frequency signal and at a second transition of the high frequency signal;
• and
• a measuring device providing a frequency, phase signal in response to the accumulated radians number signal and a preselected constant of 2π radians.

A high frequency control circuit, comprising:

• an analog to digital converter to convert a high frequency analog signal into a high frequency digitized signal;
• an equalizer to boost the amplitude of narrower pulses while introducing minimal additional inter-symbol interference of the high frequency digitized signal into a high frequency digitized, equalized signal;
• a high-pass filter to slice a direct current component from the digitized, equalized signal into a digitized, equalized and sliced high frequency signal;
• and
• a high frequency synchronization control loop including
• an all digital locked loop for recovering a bit-clock embedded in a digitized high frequency signal having
• a phase detector providing a digital output in response to a transition of the digitized high frequency signal,
• a low pass filter providing an output frequency signal in response to the digital output signal from the phase detector,
• a variable oscillator providing
• a sawtooth waveform signal ranging in phase from 0 to a predetermined multiple of 2π radians to said phase detector in response to the output frequency from said low pass filter and
• a radians number signal representing an accumulation of the number of radians provided to said phase detector immediately after a first transition of the high frequency signal and immediately before a second transition of the high frequency signal, and
• a measuring device providing a frequency, phase signal in response to the accumulated radians number signal and a preselected constant of 2π radians.