US 6,389,526 B1Granted

Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system

AssigneeAdvanced Micro Devices, Inc.

InventorsJames B. Keller, Dale Gulick, Larry Hewitt, Geoffrey Strongin

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Abstract

A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes each one of which is coupled to an individual memory. An I/O bridge coupled to a first circuit node is configured to generate non-coherent memory access command packets and non-coherent interrupt command packets. The first circuit node also generates a coherent interrupt command packet in response to receiving the non-coherent interrupt command packet. The first circuit node transmits the coherent interrupt command packet to another circuit node, possibly the second circuit node. However, the transmission of the coherent interrupt command packet may be delayed. Any delay in transmission is based on a comparison of the pipe identifications of the non-coherent command packets.

Claims20

Dependent claims

A method of operating a multiprocessor computer system comprising a plurality of circuit nodes and a plurality of memories, wherein each circuit node comprises at least one microprocessor coupled to a memory controller, wherein each memory controller is coupled to one of the plurality of memories, wherein the plurality of circuit nodes are in data communication with each other, wherein a first circuit node is coupled to an I/O bridge, the method comprising:

the I/O bridge generating a non-coherent memory access command packet, wherein the non-coherent memory access command comprises a first pipe identification;
the I/O bridge transmitting the non-coherent memory access command packet to the first circuit node via a non-coherent link connected between the I/O bridge and the first circuit node;
the first circuit node receiving the non-coherent memory access command packet and generating a coherent memory access command packet using information in the received non-coherent memory access command packet;
the first circuit node transmitting the non-coherent memory access command packet to a second circuit node;
the I/O bridge generating a non-coherent interrupt command packet, wherein the non-coherent interrupt command comprises a second pipe identification;
the I/O bridge transmitting the non-coherent interrupt command packet to the first circuit node via the non-coherent link connected between the I/O bridge and the first circuit node;
the first circuit node receiving the non-coherent interrupt command packet and generating a coherent interrupt command packet using information in the received non-coherent interrupt command packet;
comparing the first and second pipe identifications after the first circuit node receives the non-coherent interrupt command packet;
the first circuit transmitting the coherent interrupt command packet to a third circuit node if the first and second pipe identifications do not compare equally.

6 more elements

A multiprocessor computer system comprising:

a plurality of node circuits each one of which comprises at least one microprocessor in data communication with a memory controller, and wherein the plurality of node circuits are in data communication with each other;
a plurality of memories each one of which is in data communication with one of the memory controllers
an input/output (I/O) bridge circuit in data communication with a first node circuit, wherein the I/O bridge circuit is configured to sequentially generate a non-coherent memory access command packet and a non-coherent interrupt command packet, wherein the non-coherent memory access command packet contains a first pipe identification, and wherein the non-coherent interrupt command packet contains a second pipe identification;
wherein the first node circuit is configured to generate a coherent memory access command packet and a coherent interrupt command packet in response to the first circuit node receiving the non-coherent memory access command packet and the non-coherent interrupt command packet;
wherein the first node circuit is configured to transmit the coherent memory access command packet to a second circuit node;
wherein the first node circuit further a compare circuit for comparing the first and second pipe identifications;
wherein the first node circuit is configured to transmit the coherent interrupt command packet if the first and second pipe identifications do not compare equally.

4 more elements

Dependencies are inferred from the claim text.