Decoding device with associative memory permitting variable-length keyword comparisons

A variable-length code decoding device for decoding variable-length code data, comprising:

• a retrieval data setting circuit receiving a bit stream of the variable-length code data input as a decoding target, and outputting retrieval data including a fixed number of bits being decoded in one decoding process;
• an associative memory circuit responsive to input of said retrieval data for outputting decoded data corresponding to said variable-length code data and code length data indicating the number of bits of said decoded data,
• said associative memory circuit including
• a keyword comparison array retaining coded said variable-length code data as a plurality of tag data and performing a matching operation between said retrieval data input and each of said plurality of tag data,
• said keyword comparison array including a plurality of matching circuits provided corresponding to said plurality of tag data, each comparing said retrieval data and corresponding one of said plurality of tag data,
• each of said plurality of matching circuits having
• m (m is a natural number) first comparison memory units provided corresponding to a plurality of parts each including at least one bit of corresponding said tag data,
• each of said first comparison memory units retaining the at least one bit of corresponding one of said plurality of parts of said tag data and a comparison condition signal externally supplied in advance, for performing a matching operation between the retaining at least one bit and corresponding at least one bit of said retrieval data, a matching result of which being invalidated dependent on said comparison condition signal,
• said keyword comparison array further including a plurality of matching detection signal lines provided corresponding to said plurality of matching circuits,
• each of said plurality of matching detection signal lines having a potential level determined according to said matching results of (m−k) (k is an integer between 0 and m) out of said m first comparison memory units other than the k units having said matching results invalidated, included in corresponding said matching circuit, and
• said associative memory circuit further including a data storage array responsive to the potential level of each of said plurality of matching detection signal lines for outputting said decoded data and said code length data associated wit h said variable-length code data corresponding to one of said plurality of tag data;
• and
• a decoding target pointer circuit responsive to said code length data for designating to said retrieval data setting circuit a leading bit of the fixed number of bits, of the bit stream of said variable-length code data input, to be decoded in a next decoding process.

A variable-length code decoding device for decoding variable-length code data, comprising:

• a retrieval data setting circuit receiving a bit stream of the variable-length code data input as a decoding target, and outputting retrieval data including a fixed number of bits being decoded in one decoding process;
• an associative memory circuit responsive to input of said retrieval data for outputting decoded data corresponding to said variable-length code data and code length data indicating the number of bits of said decoded data,
• said associative memory circuit including
• a keyword comparison array retaining coded said variable-length code data as a plurality of tag data and performing a matching operation between said retrieval data input and each of said plurality of tag data,
• said keyword comparison array including a plurality of matching circuits provided corresponding to said plurality of tag data, each for comparing said retrieval data and corresponding one of said plurality of tag data,
• each of said plurality of matching circuits having
• n (n is an integer at least 0) first comparison memory units provided corresponding to n bits of said corresponding tag data, each retaining corresponding one of said n bits and performing a matching operation between the retaining bit and a corresponding bit of said retrieval data, and
• m (m is a natural number) second comparison memory units provided corresponding to a plurality of parts each including at least one bit of remaining bits of said corresponding tag data other than said n bits, each performing said matching operation between the at least one bit of corresponding one of said plurality of parts of the remaining bits and corresponding at least one bit of said retrieval data, a matching result of which being invalidated dependent on an externally set comparison condition signal,
• said keyword comparison array further including a plurality of matching detection signal lines provided corresponding to said plurality of matching circuits,
• each of said plurality of matching detection signal lines having a potential level determined according to the matching results of said n first comparison memory units and the matching results of (m−k) (k is an integer from 0 to m) out of said m second comparison units other than the k units having said comparison results invalidated, included in corresponding said matching circuit,
• said associative memory circuit further including a data storage array responsive to the potential level of each of said plurality of matching detection signal lines for outputting said decoded data and said code length data associated with said variable-length code data corresponding to one of said plurality of tag data;
• and
• a decoding target pointer circuit responsive to said code length data for designating to said retrieval data setting circuit a leading bit of the fixed number of bits, of the bit stream of said variable-length code data input, to be decoded in a next decoding process.