Signal control circuit for controlling signals to and from a subsidiary processing circuit

A method for performing a block floating point FFT on a plurality of data values having absolute values utilizing a processor executing a program, the processor including an execution unit, a compare absolute value unit, a scale down by 2 unit, a scale-before-store bit for enabling a scale-before-store mode, a user-loadable FFT compare register, and an FFT sticky status bit, the method comprising the steps of:

• (a) activating, if the scale-before-store mode is enabled, the scale down by 2 unit;
• (b) comparing each of the plurality of data values with the FFT compare register;
• (c) setting, if a data value absolute value is not less than the FFT compare register, the FFT sticky status bit;
• and
• (d) enabling, if the FFT sticky status bit is set, the scale-before-store mode.

A signal control circuit, provided between a main processing circuit for outputting an address signal to designate an address and a dynamic RAM that performs data reading operation and data writing operation to the address designated by the address signal outputted from the main processing circuit, the signal control circuit being for receiving the address signal from the main processing circuit, for dividing the address signal into row address and column address, for outputting the row address and column address in a predetermined order to the dynamic RAM while outputting, to the dynamic RAM, a control signal for controlling timings when the dynamic RAM reads the row address and the column address, the control signal circuit comprising:

• a comparing portion that compares, when column address, included in a present address signal outputted from the main processing circuit at a present time, is to be outputted subsequent to row address included in the present address signal, each bit at least in a predetermined portion of the column address with a corresponding bit at least in the predetermined portion of the row address, and that compares, when column address, included in the present address signal, is to be outputted subsequent to another column address included in a preceding address signal that is outputted from the main processing circuit at a preceding time, each bit at least in a predetermined portion of the column address included in the present address signal with a corresponding bit at least in the predetermined portion of the column address included in the preceding address signal, the comparing portion outputting a delay request signal when a predetermined difference occurs between the compared addresses;
• and
• an output control portion that outputs, at a predetermined timing, a control signal for controlling the timing when the dynamic RAM reads the column address in the present address signal when the compared results show that the predetermined difference does not occur between the addresses compared by the comparing portion, the output control portion delaying, from the predetermined timing, the timing for outputting the control signal when the output control portion receives the delay request signal indicating that the predetermined difference occurs between the addresses compared by the comparing portion, thereby preventing the reading operation of the column address in the present address signal from being influenced from noise that occurs when the address changes from the row address in the present address signal into the column address in the present address signal while occurring the predetermined difference and from noise that occurs when the address changes from the column address in the preceding address signal into the column address in the present address signal while occurring the predetermined difference.

A signal control system, comprising:

• a main processing circuit for mainly processing a bus signal;
• a subsidiary processing circuit capable of communicating the bus signals with the main processing circuit via a bus;
• and
• a signal control circuit, provided between the main processing circuit and the subsidiary processing circuit, the signal control circuit including:
• means for receiving the bus signals that are successively inputted to or outputted from the subsidiary processing circuit, and
• means for outputting control signals to the subsidiary processing circuit, thereby controlling at least one of input and output of the bus signals to and from the subsidiary processing circuit;
• and
• means for comparing at least a predetermined portion in all of a plurality of bits constituting a present bus signal, which is inputted to or outputted from the subsidiary processing circuit at a present timing, with at least the predetermined portion in all of a plurality of bits constituting a preceding bus signal, which is inputted to or outputted from the subsidiary processing circuit at a timing preceding to the present timing, the comparing means instructing the control signal outputting means to output, at a predetermined timing, the control signal, for controlling a corresponding one of input and output of the present bus signal, to the subsidiary processing circuit when the compared result shows that a predetermined difference does not occur between the present bus signal and the preceding bus signal, the comparing means outputting a delay request signal to the control signal outputting means to delay, from the predetermined timing, the output of the control signal when the compared result shows that the predetermined difference occurs between the present bus signal and the preceding bus signal, thereby preventing the at least one of input and output operation of the present bus signal from being influenced from noise that occurs when the bus signal changes from the preceding bus signal into the present bus signal while occurring the predetermined difference.

A dynamic Ram control system, comprising:

• a main processing circuit for outputting an address signal to designate an address;
• a dynamic RAM that performs data reading operation and data writing operation to the address designated by the address signal outputted from the main processing circuit;
• and
• a signal control circuit, provided between the main processing circuit and the dynamic RAM, for receiving the address signal from the main processing circuit, the signal control circuit including:
• means for receiving address signals successively outputted from main processing circuit, for dividing each received address signal into row address and column address, for outputting at least one of the row address and the column address in a predetermined order to dynamic RAM, while outputting, to the dynamic RAM, a control signal for controlling a timing when the dynamic RAM reads the outputted at least one of the row address and the column address;
• and
• means for, when the output means outputs column address, included in a present address signal that is received from the main processing circuit at a present time, next to row address included also in the present address signal, comparing each bit at least in a predetermined portion of the column address with a corresponding bit at least in the predetermined portion of the row address, and for, when the output means outputs column address, included in the present address signal, next to another column address including in a preceding address signal that is outputted from the main processing circuit at a timing preceding to the present timing, comparing each bit at least in a predetermined portion of the column address included in the present address signal with a corresponding bit at least in the predetermined portion of the column address included in the preceding address signal, the comparing means failing to output a delay request signal to the output means when the compared results show that a predetermined difference does not occur between the addresses compared by the comparing portion, thereby controlling the output means to output, at a predetermined timing, the control signal for controlling a timing when the dynamic RAM is to read the column address that is included in the present address signal, the comparing means outputting the delay request signal to the output means when the compared results show that the predetermined difference occurs between the addresses compared by the comparing portion, thereby controlling the output means to delay, from the predetermined timing, the output of the control signal, thereby preventing the reading operation of the column address in the present address signal from being influenced from noise that occurs when the address changes from the row address in the present address signal into the column address in the present address signal while occurring the predetermined difference and from noise that occurs when the address changes from the column address in the preceding address signal into the column address in the present address signal while occurring the predetermined difference.