Data transfer control of a video memory having a multi-divisional random access memory and a multi-divisional serial access memory

A memory comprising:

• a memory array, partitioned into N (N=2n, n is an integer;
• N is an integer of 2 or greater) divisional memory areas, each of said divisional memory areas including a plurality of memory cells arranged in a matrix, cells at the same row of the matrix in a divisional memory area being accessed simultaneously;
• a serial access memory (SAM) array partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) divisional SAM areas serially accessed asynchronously with said memory array, each of said divisional SAM areas corresponding to one of said divisional memory areas and temporarily storing data from cells of one row of said matrix of the divisional memory areas;
• and
• a data transfer unit to transfer data between one divisional memory area of said memory array and its corresponding divisional SAM area of said serial access memory array;
• wherein if data corresponding to a boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a divisional SAM area being serially accessed, a data transfer from one of the divisional memory areas to the divisional SAM area is neglected.

A memory comprising:

• a memory array, partitioned into N (N=2n, n is an integer;
• N is an integer of 2 or greater) divisional memory areas, each of said divisional memory areas including a plurality of memory cells arranged in a matrix, cells at the same row of the matrix in a divisional memory area being accessed simultaneously;
• a serial access memory (SAM) array partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) divisional SAM areas serially accessed asynchronously with said memory array, each of said divisional SAM areas corresponding to one of said divisional memory areas and temporarily storing data from cells of one row of said matrix of the divisional memory areas;
• and
• a data transfer unit to transfer data between one divisional memory area of said memory array and its corresponding divisional SAM area of said serial access memory array;
• wherein if data corresponding to a boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a divisional SAM area being serially accessed, boundary address bits for designating the divisional SAM area being serially accessed are neglected and an address of a next divisional SAM area is designated.

A memory comprising:

• a first memory array, partitioned into N (N=2n, n is an integer, N is an integer of 2 or greater) first divisional memory areas, each of said first divisional memory areas including a plurality of memory cells arranged in a matrix, cells of the first memory array having a same row address commonly designated in the first divisional memory areas being accessed simultaneously;
• a second memory array, partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) second divisional memory areas continuously accessed asynchronously with respect to said first memory array, each of said second divisional memory areas temporarily storing data from cells of one row of said matrix of the first divisional memory areas, said second memory array being accessed in an arbitrary sequential order using a boundary address for initiating a serial transfer cycle;
• and
• a data transfer unit to transfer data from one of the first divisional memory areas of said first memory array to any one of the second divisional memory areas of said second memory array,
• wherein continuous access is executed reading one of said second divisional memory areas, and
• wherein if data corresponding to the boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a second divisional memory area being serially accessed, a data transfer timing from one of the first divisional memory areas to the second divisional memory area and an output timing from the second divisional memory area are synchronized.

A memory comprising:

• a first memory array, partitioned into N (N=2n, n is an integer, N is an integer of 2 or greater) first divisional memory areas, each of said first divisional memory areas including a plurality of memory cells arranged in a matrix, cells of the first memory array having a same row address commonly designated in the first divisional memory areas being accessed simultaneously;
• a second memory array, partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) second divisional memory areas continuously accessed asynchronously with respect to said first memory array, each of said second divisional memory areas temporarily storing data from cells of one row of said matrix of the first divisional memory areas, said second memory array being accessed in an arbitrary sequential order using a boundary address for initiating a serial transfer cycle;
• and
• a data transfer unit to transfer data from one of the first divisional memory areas of said first memory array to any one of the second divisional memory areas of said second memory array,
• wherein continuous access is executed by reading one of said second divisional memory areas, and
• wherein if data corresponding to the boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a second divisional memory area being serially accessed, a data transfer from one of the first divisional memory areas to the second divisional memory area is neglected.

A memory comprising:

• a first memory array, partitioned into N (N=2n, n is an integer, N is an integer of 2 or greater) first divisional memory areas, each of said first divisional memory areas including a plurality of memory cells arranged in a matrix, cells of the first memory array having a same row address commonly designated in the first divisional memory areas being accessed simultaneously;
• a second memory array, partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) second divisional memory areas continuously accessed asynchronously with respect to said first memory array, each of said second divisional memory areas temporarily storing data from cells of one row of said matrix of the first divisional memory areas, said second memory array being accessed in an arbitrary sequential order using a boundary address for initiating a serial transfer cycle;
• and
• a data transfer unit to transfer data from one of the first divisional memory areas of said first memory array to any one of the second divisional memory areas of said second memory array,
• wherein continuous access is executed by reading one of said second divisional memory areas, and
• wherein if data corresponding to the boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a second divisional memory area being serially accessed, boundary address bits for designating the second divisional memory area being serially accessed are neglected and an address of a next second divisional memory area is designated.

A method for reading data in a memory, said memory including a memory array, partitioned into N (N=2n, n is an integer, N is an integer of 2 or greater) divisional memory areas, each of said divisional memory areas including a plurality of memory cells arranged in a matrix, cells at a same row of the matrix in a divisional memory area being accessed simultaneously;

• and a serial access memory (SAM) array partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) divisional SAM areas serially accessed asynchronously with said memory array, each of said divisional SAM areas corresponding to one of said divisional memory areas and temporarily storing data from cells of one row of said matrix of the divisional memory areas;
• wherein said method comprises the steps of:
• transferring data in one of said N divisional memory areas to a corresponding one of M divisional SAM areas, and
• reading data in the divisional SAM areas where data has been transferred from a corresponding divisional memory area, said reading being performed such that when present reading reaches a boundary address of a divisional SAM area, a next reading starts from an address in another divisional SAM area, which is designated during the present reading in the divisional SAM area,
• wherein if data corresponding to the boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a divisional SAM area being serially accessed, a data transfer timing from one of the divisional memory areas to the divisional SAM area and an output timing from the divisional SAM area are synchronized.

A method for reading data in a memory, said memory including a memory array, partitioned into N (N=2n, n is an integer, N is an integer of 2 or greater) divisional memory areas, each of said divisional memory areas including a plurality of memory cells arranged in a matrix, cells at a same row of the matrix in a divisional memory area being accessed simultaneously;

• and a serial access memory (SAM) array partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) divisional SAM areas serially accessed asynchronously with said memory array, each of said divisional SAM areas corresponding to one of said divisional memory areas and temporarily storing data from cells of one row of said matrix of the divisional memory areas;
• wherein said method comprises the steps of:
• transferring data in one of said N divisional memory areas to a corresponding one of M divisional SAM areas, and
• reading data in the divisional SAM areas where data has been transferred from a corresponding divisional memory area, said reading being performed such that when present reading reaches a boundary address of a divisional SAM area, a next reading starts from an address in another divisional SAM area, which is designated during the present reading in the divisional SAM area,
• wherein if data corresponding to the boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a divisional SAM area being serially accessed, a data transfer from one of the divisional memory areas to the divisional SAM area is neglected.

A method for reading data in a memory, said memory including a memory array, partitioned into N (N=2n, n is an integer, N is an integer of 2 or greater) divisional memory areas, each of said divisional memory areas including a plurality of memory cells arranged in a matrix, cells at a same row of the matrix in a divisional memory area being accessed simultaneously;

• and a serial access memory (SAM) array partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) divisional SAM areas serially accessed asynchronously with said memory array, each of said divisional SAM areas corresponding to one of said divisional memory areas and temporarily storing data from cells of one row of said matrix of the divisional memory areas;
• wherein said method comprises the steps of:
• transferring data in one of said N divisional memory areas to a corresponding one of M divisional SAM areas, and
• reading data in the divisional SAM areas where data has been transferred from a corresponding divisional memory area, said reading being performed such that when present reading reaches a boundary address of a divisional SAM area, a next reading starts from an address in another divisional SAM area, which is designated during the present reading in the divisional SAM area,
• wherein if data corresponding to the boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a divisional SAM area being serially accessed, boundary address bits for designating the divisional SAM area being serially accessed are neglected and an address of a next divisional SAM area is designated.

A method for reading data in a memory, said memory including a first memory array, partitioned into N (N=2n, n is an integer;

• N is an integer of 2 or greater) first divisional memory areas, each of said first divisional memory areas including a plurality of memory cells arranged in a matrix, cells at the same row of the matrix in a first divisional memory area being accessed simultaneously;
• and a second memory array partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) second divisional memory areas continuously accessed asynchronously with respect to said first memory array, each of said second divisional memory areas temporarily storing data from cells of one row of said matrix of the first divisional memory areas;
• wherein said method comprises the steps of:
• transferring data in one of said N first divisional memory areas to a corresponding one of the M second divisional memory areas, and
• reading data in second divisional memory areas where data has been transferred from corresponding first divisional memory areas, said reading being performed such that when present reading reaches a boundary address of a second divisional memory area, access of the second divisional memory area jumps to another second divisional memory area to start a new access;
• wherein if data corresponding to the boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a second divisional memory area being serially accessed, a data transfer timing from one of the first divisional memory areas to the second divisional memory area and an output timing from the second divisional memory area are synchronized.

A method for reading data in a memory, said memory including a first memory array, partitioned into N (N=2n, n is an integer;

• N is an integer of 2 or greater) first divisional memory areas, each of said first divisional memory areas including a plurality of memory cells arranged in a matrix, cells at the same row of the matrix in a first divisional memory area being accessed simultaneously;
• and a second memory array partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) second divisional memory areas continuously accessed asynchronously with respect to said first memory array, each of said second divisional memory areas temporarily storing data from cells of one row of said matrix of the first divisional memory areas;
• wherein said method comprises the steps of:
• transferring data in one of said N first divisional memory areas to a corresponding one of the M second divisional memory areas, and
• reading data in second divisional memory areas where data has been transferred from corresponding first divisional memory areas, said reading being performed such that when present reading reaches a boundary address of a second divisional memory area, access of the second divisional memory area jumps to another second divisional memory area to start a new access;
• wherein if data corresponding to the boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a second divisional memory area being serially accessed, a data transfer from one of the first divisional memory areas to the second divisional memory area is neglected.

A method for reading data in a memory, said memory including a first memory array, partitioned into N (N=2n, n is an integer;

• N is an integer of 2 or greater) first divisional memory areas, each of said first divisional memory areas including a plurality of memory cells arranged in a matrix, cells at the same row of the matrix in a first divisional memory area being accessed simultaneously;
• and a second memory array partitioned into M (M=2m, m is an integer greater than or equal to 2;
• M is an integer of 4 or greater) second divisional memory areas continuously accessed asynchronously with respect to said first memory array, each of said second divisional memory areas temporarily storing data from cells of one row of said matrix of the first divisional memory areas;
• wherein said method comprises the steps of:
• transferring data in one of said N first divisional memory areas to a corresponding one of the M second divisional memory areas, and reading data in second divisional memory areas where data has been transferred from corresponding first divisional memory areas, said reading being performed such that when present reading reaches a boundary address of a second divisional memory area, access of the second divisional memory area jumps to another second divisional memory area to start a new access;
• wherein if data corresponding to the boundary address designated during a first transfer cycle for initiating a second transfer cycle is in a second divisional memory area being serially accessed, boundary address bits for designating the second divisional memory area being serially accessed are neglected and an address of a next second divisional memory area is designated.