Method and apparatus for providing probe based bus locking and address locking

A method for facilitating access to shared memory addresses over a common bus by a plurality of data processors comprising the steps of:

• detecting, by at least a first data processor, that two access addresses are boundary addresses on either side of an address boundary;
• locking the common bus in response to detecting the two access addresses;
• generating, by the first processor, address probe inquiry data for at least one of the boundary addresses wherein the address probe inquiry data includes data representing an address to be probed and data representing an inquiry as to whether the address to be probed is available for future use by the first processor;
• locking the two detected access addresses based on the address probe inquiry data communicated by the first processor to at least a second processor;
• and
• removing the bus lock when the address lock is achieved for both boundary addresses.

An apparatus for facilitating access to shared memory addresses over a common bus by a plurality of data processors comprising:

• means for detecting that two access addresses are boundary addresses on either side of an address boundary;
• means for locking the common bus in response to detecting the two access addresses;
• and
• means for locking the two detected access addresses based on address probe inquiry data communicated by the first processor to at least a second processor.