Multiprocessor system and methods for transmitting memory access transactions for the same

A processor system containing a plurality of processor nodes, and a network for coupling said plurality of processor nodes with each other, each of said plural processor nodes including both a memory for constituting a main memory and also at least one processor unit which contains a cache for temporarily storing a portion of a memory block of said main memory;

• wherein:
• each of said processor nodes is comprised of:
• first means for specifying a processor node having a memory to which an address to be accessed is allocated as a target node in response to such a fact that a main memory access request is produced in a processor unit contained in the own processor node, and for issuing a first sort of command to said target node;
• second means for judging as to whether or not there is such a possibility that the memory block containing the address to be accessed is stored into a cache of another node-in response to said main memory access request;
• for issuing a second sort of command to said target node when said judgement result is “no possibility”;
• and for distributing said second sort of command to all of the processor nodes other than the own processor node so as to execute a cache united control when said judgement result is “possibility”;
• and
• third means for inputting a portion of an access address into said memory based upon said first sort of command received from another processor node;
• and for inputting at least the remaining portion of said access address into said memory when an address to be accessed which is indicated by said second sort of command received from another processor node corresponds to the memory of the own processor node so as to execute a memory access operation.

A processor system containing a plurality of processor nodes, and a network for coupling said plurality of processor nodes with each other, each of said plural processor nodes including both a memory for constituting a main memory and also at least one processor unit which contains a cache for temporarily storing a portion of a memory block of said main memory;

• wherein:
• each of said processor nodes is comprised of:
• first means for specifying a processor node having a memory to which an address to be accessed is allocated as a target node in response to such a fact that a main memory access request is produced in a processor unit contained in the own processor node, and for issuing a first command to said target node;
• an access right memory for storing such information indicating as to whether or not each of the own processor nodes has an access right with respect to a plurality of memory blocks of said main memory;
• and
• second means for retrieving said access right memory based upon the address to be accessed in response to an access request of said main memory;
• for issuing a second sort of command to said target node when said retrieved result indicates that the own processor node owns the access right;
• and for distributing said second sort of command to all processor nodes other than the own processor node in order to execute a cache united control when the retrieved result indicates that the own processor node does not own the access right, or said information is not stored into said access right memory;
• and wherein:
• the memory of each of said processor nodes is accessed in such a manner that said processor node receives said first sort of command, and thereafter a second command is received.

An integrated circuit set used to constitute a processor system containing a plurality of processor nodes, and a network for coupling said plurality of processor nodes with each other, each of said plural processor nodes including both a memory for constituting a main memory and also at least one processor unit which contains a cache for temporarily storing a portion of a memory block of said main memory, comprising:

• first means for specifying a processor node having a memory to which an address to be accessed is allocated as a target node in response to such a fact that a main memory access request is produced in a processor unit contained in the own processor node, and for issuing a first sort of command to said target node;
• second means for judging as to whether or not there is such a possibility that the memory block containing the address to be accessed is stored into a cache of another node in response to said main memory access request;
• for issuing a second sort of command to said target node when said judgement result is “no possibility”;
• and for distributing said second sort of command to all of the processor nodes other than the own processor node so as to execute a cache united control when said judgement result is “possibility”;
• and
• third means for inputting a portion of an access address into said memory based upon said first sort of command received from another processor node;
• and for inputting at least the remaining portion of said access address into said memory when an address to be accessed which is indicated by said second sort of command received from another processor node corresponds to the memory of the own processor node so as to execute a memory access operation.

In a method for transferring a transaction between a plurality of processor nodes and a memory for constituting a main memory, each of said plural processor nodes having at least one processor unit containing a cache for temporarily storing a portion of a memory block of said main memory, and said transaction being caused by a memory access request issued in one of said processor units,

• a transaction transferring method comprising the steps of:
• transferring a first transaction used to designate a portion of an address to be accessed from a source node where said memory access request is produced to a target node having a memory to which the address to be accessed of said memory access request in an one-to-one correspondence;
• transferring a second transaction to all of the processor nodes other than said source node so as to execute a global cache united control in such a case that after executing a local cache united control within said source node, there is a possibility that a memory block containing said address to be accessed is stored into a cache of a processor node other than said source node;
• and
• transferring said second transaction to said target node in such a case that there is no possibility that the memory block containing said address to be accessed is stored into the cache of the processor node other than said source node;
• wherein:
• in said target node, the remaining portion of said address to be accessed is designated by said second transaction so as to execute the access operation to said memory.

In a method for transferring a transaction among a plurality of processors having both a memory for constituting a main memory and at least one processor unit containing a cache for temporarily storing a portion of a memory block of said main memory, said transaction being caused by a memory access request issued in one of said processor units,

• a transaction transferring method comprising the steps of:
• transferring a first transaction used to designate a portion of an address to be accessed from a source node where said memory access request is produced to a target node having a memory to which the address to be accessed of said memory access request in an one-to-one correspondence;
• transferring a second transaction to all of the processor nodes other than said source node so as to execute a global cache united control in such a case that after executing a local cache united control within said source node, there is a possibility that a memory block containing said address to be accessed is stored into a cache of a processor node other than said source node;
• and
• transferring said second transaction to said target node in such a case that there is no possibility that the memory block containing said address to be accessed is stored into the cache of the processor node other than said source node;
• wherein:
• in said target node, the remaining portion of said address to be accessed is designated by said second transaction so as to execute the access operation to said memory.