Method and computer system for speculatively closing pages in memory
AssigneeHewlett-Packard Company
InventorTomas G. Rokicki
Life of this patent
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Abstract
The present invention provides a method and an apparatus for addressing a main memory unit in a computer system which results in improved page hit rate and reduced memory latency by only keeping open some recently used pages and speculatively closing the rest of the pages in the main memory unit. In a computer system with 64 banks and 2 CPUs, only 8 banks may be kept open and the remaining 56 banks are kept closed. Keeping only 8 banks open will not reduce the page hit frequency significantly, but will allow most accesses that are not page hits to access banks that are already closed, so that they are not slowed down by open banks. Thus, the page hit rate is increased and the miss rate is reduced.
Claims20
A computer system comprising:
- a processor that generates a logical address to facilitate memory accesses, said logical address includes bank index bits;
- a main memory unit that is organized in banks, rows and columns, said main memory unit is addressed via bank, row and column bits, wherein each bank includes a plurality of rows;
- and
- a memory controller coupled between said processor and said main memory unit, wherein said memory controller:
- generates from said logical address the bank, row, and column bits required by the main memory unit, and said bank index bits are used to generate said bank bits, and
- includes a plurality of bank controllers that are addressed by said bank bits, said bank bits are maintained in a queue, said queue is operable to select a predetermined number of bank controllers.
A method of accessing a main memory unit using a logical address generated by a processor in a computer system, wherein the main memory unit is organized in banks, rows and columns and is addressed via bank, row and column bits, wherein each bank includes a plurality of rows, and wherein the computer system includes a memory controller coupled between the processor and the main memory unit, the memory controller includes a plurality of bank controllers that are addressed by the bank bits, the bank bits are maintained in a queue, the method comprising:
- selecting a predetermined number of bank controllers, each selected bank controller opens a corresponding bank, each opened bank opens one of the plurality of rows;
- and
- maintaining the bank bits of said predetermined number of bank controllers using the queue.
Dependencies are inferred from the claim text.