Microprocessor configured to detect updates to instructions outstanding within an instruction processing pipeline and computer system including same

A computer system comprising:

• an input/output (I/O) device configured to communicate between said computer system and another computer system to which said I/O device is couplable;
• a memory;
• and
• a microprocessor coupled to said memory, said microprocessor including:
• an instruction processing pipeline;
• and
• an instruction cache coupled to supply instructions to said instruction processing pipeline, wherein said instruction cache includes a buffer configured to store a plurality of addresses, wherein each of said plurality of addresses corresponds to at least two cache lines, said at least two cache lines corresponding to consecutive memory locations within said memory, and wherein said plurality of addresses encompasses instructions outstanding within said instruction processing pipeline, and wherein said instruction cache is coupled to receive a first address indicative of a first memory location of said memory which is being updated, and wherein said instruction cache is configured to cause said instruction processing pipeline to flush one or more instructions responsive to said plurality of addresses encompassing said first memory location.