Apparatus for flexibly allocating request/grant pins between multiple bus controllers

An apparatus that flexibly allocates I/O pins used for bus grant signals between bus controllers, comprising:

• a semiconductor chip;
• a first bus arbitration circuit located on the semiconductor chip;
• a second bus arbitration circuit located on the semiconductor chip;
• a first set of grant lines emanating from the first bus arbitration circuit, the first set of grant lines being used to grant control of a first bus to devices on the first bus, the first set of grant lines being divided into a first subset of grant lines and a second subset of grant lines;
• a second set of grant lines emanating from the second bus arbitration circuit, the second set of grant lines being used to grant control of a second bus to devices on the second bus, the second set of grant lines being divided into a third subset of grant lines and a fourth subset of grant lines;
• a selector circuit that selects a plurality of outputs from between the first subset of grant lines and the third subset of grant lines, the plurality of outputs being coupled to a first set of output pins on the semiconductor chip;
• wherein the selector circuit is configured to select the first subset of grant lines to be driven through the first set of output pins during a first mode of operation, and is configured to select the third subset of grant lines to driven through the first set of output pins during a second mode of operation;
• wherein the second subset of grant lines is coupled to a second set of output pins, and the fourth subset of grant lines is coupled to a third set of output pins;
• and
• a set of request lines coupled to input pins of the semiconductor chip, the set of request lines being divided into a first subset of request lines, a second subset of request lines and a third subset of request lines;
• wherein the first subset of request lines is coupled to the first bus arbitration circuit, the second subset of request lines is coupled to the second bus arbitration circuit, and the third subset of request lines is coupled to the first bus arbitration circuit and the second bus arbitration circuit.

A computer system that flexibly allocates I/O pins used for bus grant signals between bus controllers, comprising:

• a processor;
• a memory;
• a core logic chip;
• a first bus arbitration circuit located on the core logic chip;
• a second bus arbitration circuit located on the core logic chip;
• a first set of grant lines emanating from the first bus arbitration circuit, the first set of grant lines being used to grant control of a first bus to devices on the first bus, the first set of grant lines being divided into a first subset of grant lines and a second subset of grant lines;
• a second set of grant lines emanating from the second bus arbitration circuit, the second set of grant lines being used to grant control of a second bus to devices on the second bus, the second set of grant lines being divided into a third subset of grant lines and a fourth subset of grant lines;
• and
• a selector circuit that selects a plurality of outputs from between the first subset of grant lines and the third subset of grant lines, the plurality of outputs being coupled to a first set of output pins on the core logic chip;
• wherein the selector circuit is configured to select the first subset of grant lines to be driven through the first set of output pins during a first mode of operation, and is configured to select the third subset of grant lines to driven through the first set of output pins during a second mode of operation.