US 6,389,490 B1 · FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals

Abstract

A first in, first out (FIFO) memory system and method in which the full or empty condition of the FIFO memory is detected before the FIFO memory is actually full or empty, thereby allowing the generation of FULL or EMPTY control signals immediately after a last data value is written into or from the FIFO memory. An almost-empty condition, is detected by comparing the read address and write address values. When the read and write address values indicate that one data value remains in the FIFO memory and a read operation is about to be performed, an ALMOST_EMPTY control signal is applied to a data input terminal of a first register that is clocked by a read clock signal. The ALMOST_EMPTY control signal is latched by the first register at the next rising edge of a read clock signal, thereby causing the register to generate a high EMPTY control signal in the same read clock cycle during which the last data value is read from the FIFO memory. Similarly, an almost-full condition, is also detected by comparing the read address and write address values. By preventing a write address counter from “catching up” to a read address counter, the determination of FULL and EMPTY conditions is greatly simplified. The FIFO memory system may also include binary-to-Gray-code converters as well as a write synchronization circuit for synchronizing a binary read address to a write clock signal to provide an accurate indication of the amount of data stored in the FIFO memory.

Claims23

Dependent claims

A first in, first out (FIFO) memory system, comprising:

a memory having a plurality of locations each having an address, a write address port for receiving a sequence of write address values during write operations, and a read address port for receiving a sequence of read address values during read operations;
and
a flag control circuit including:
a first multi-bit comparator for detecting an almost-empty condition, which occurs when only one data value is stored in the memory, by comparing a first read address value associated with the sequence of read address values to a first write address value associated with the sequence of write address values;
a first logic circuit connected to an output terminal of the first multi-bit comparator, wherein the first logic circuit asserts an ALMOST_EMPTY control signal on an output terminal when the first multi-bit comparator detects the almost-empty condition during a read operation;
and
a register for asserting an EMPTY control signal when there are no data values stored in the memory, the register having a data input terminal coupled to the output terminal of the first logic circuit, and a clock input terminal connected to receive a clock signal;
wherein the register latches the ALMOST_EMPTY control signal immediately after the ALMOST_EMPTY control signal is asserted by the first logic circuit, thereby causing the register to assert the EMPTY control signal during the same clock cycle of the clock signal in which said only one data value is read from the memory.

5 more elements

A first in, first out (FIFO) memory system, comprising:

a memory having a plurality of locations each having an address, a write address port for receiving a sequence of write address values during write operations, and a read address port for receiving a sequence of read address values during read operations;
and
a flag control circuit including:
a first multi-bit comparator for detecting an almost-full condition, which occurs when data values are stored in all but a last location of the memory, by comparing a first read address value associated with the sequence of read address values to a first write address value associated with the sequence of write address values;
a first logic circuit connected to an output terminal of the first multi-bit comparator, wherein the first logic circuit asserts an ALMOST_FULL control signal on an output terminal when the first multi-bit comparator detects the almost-full condition during a write operation;
and
a register for asserting a FULL control signal when data values are stored in all locations of the memory, the register having a data input terminal coupled to the output terminal of the first logic circuit, and a clock input terminal connected to receive a clock signal;
wherein the register latches the ALMOST_FULL control signal immediately after the ALMOST_FULL control signal is asserted by the first logic circuit, thereby causing the register to assert the FULL control signal during the same clock cycle of the clock signal in which a data value is written to said last location of the memory.

5 more elements

A first in, first out (FIFO) memory system, comprising:

a memory having a plurality of locations each having an address, a write address port for receiving a sequence of write address values during write operations, and a read address port for receiving a sequence of read address values during read operations;
and
a flag control circuit including:
first means for detecting an almost-empty condition, which occurs when only one data value is stored in the memory, by comparing a first read address value associated with the sequence of read address values to a first write address value associated with the sequence of write address values, and for asserting an ALMOST_EMPTY control signal on an output terminal when the almost-empty condition is detected during a read operation;
a first register for asserting an EMPTY control signal when there are no data values stored in the memory, the register having a data input terminal coupled to the output terminal of the first means, and a clock input terminal connected to receive a read clock signal;
second means for detecting an almost-full condition, which occurs when data values are stored in all but a last location of the memory, by comparing a second read address value associated with the sequence of read address values to a second write address value associated with the sequence of write address values, and for asserting an ALMOST_FULL control signal on an output terminal when the almost-full condition is detected during a write operation;
and
a second register for asserting a FULL control signal when data values are stored in all locations of the memory, the register having a data input terminal coupled to the output terminal of the second means, and a clock input terminal connected to receive a write clock signal;
wherein the first register latches the ALMOST_EMPTY control signal immediately after the ALMOST_EMPTY control signal is asserted by the first means, thereby causing the first register to assert the EMPTY control signal during the same clock cycle of the read clock signal in which said one data value is read from the memory, and
wherein the second register latches the ALMOST_FULL control signal immediately after the ALMOST_FULL control signal is asserted by the second means, thereby causing the second register to assert the FULL control signal during the same clock cycle of the write clock signal in which a data value is written to said last location of the memory.

7 more elements

Dependencies are inferred from the claim text.

FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals

Life of this patent

FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals

Life of this patent

Abstract

Claims23