Adder apparatus having single adder for +1 and +2 functions

An adder apparatus for receiving an n-bit input signal and a control signal to generate an (n+1)-bit output signal, comprising:

• a first logic circuit for performing a NOR operation upon a first bit of said n-bit input signal and said control signal to generate a first signal;
• a second logic circuit for performing an OR operation upon the first bit of said n-bit input signal and said control signal to generate a logic OR signal and performing a NAND operation upon said logic OR signal and a second bit of said n-bit input signal to generate a second signal;
• a plurality of third logic circuits each for performing a NAND operation upon an (i−1)th (i=3, 4, . . . , n) bit of said n-bit input signal and i-th bit of said n-bit input signal to generate a third signal;
• a carry signal generating circuit, connected to said first, second and third logic circuits, for receiving said first, second and third signals to generate “n” carry signals;
• and
• a sum generation circuit, connected to said carry signal generating circuit, for receiving said n-bit input signal, said “n” carry signals and said control signal to generate said (n+1)-bit output signal,
• said sum generation circuit comprising a fourth logic circuit for performing an exclusive NOR operation upon the first bit of said n-bit input signal and said control signal to generate a first bit of said (n+1)-bit output signal.