Method for simulation of pipeline processor using passing operation
AssigneeFujitsu Limited
InventorsRyuta Tanaka, Norichika Kumamoto
Life of this patent
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Abstract
A simulator can simulate a processor which performs pipeline processing of operation instructions, and performs operation processes in parallel, a number of the processes being larger than a number of the pipelines. The simulator simulates a passing operation in which a result of an operation processing obtained from execution of an operation instruction is output earlier than a result of another operation process obtained from previously started execution of another operation instruction, the passing operation occurring due to the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions.
Claims17
A simulator, which can simulate a processor which performs pipeline processing of operation instructions, and performs operation processes in parallel, a number of the operation processes being larger than a number of the pipelines,
- wherein said simulator simulates a passing operation in which a result of an operation process obtained from execution of an operation instruction is output earlier than a result of another operation process obtained from previously started execution of another operation instruction, the passing operation occurring due to the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions.
A simulation method for simulating a processor which performs pipeline processing of operation instructions, starts operation processes in an order in which the operation instructions are input, performs the operation processes in parallel, and outputs results of the operation processes in an order in which the operation processes are finished,
- wherein said method comprises the step of a) detecting a passing operation in which a result of the operation process obtained from execution of an operation instruction is output earlier than a result of another operation process obtained from previously started execution of another operation instruction the passing operation occurring due to the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions.
A computer readable recording medium storing a program for causing a computer to perform simulation of a processor which performs pipeline processing of operation instructions,
- said program causing the computer to simulate a passing operation in which a result of the operation process obtained from execution of an operation instruction is output earlier than a result of another operation process obtained from previously started execution of another operation instruction, the passing operation occurring due to the number of execution cycles of each operation instruction which is executed in parallel with execution of other operation instructions.
Dependencies are inferred from the claim text.