US 6,389,315 B1 · Implantable medical device incorporating self-timed logic

Abstract

Improved operating system architecture for an implantable medical device incorporating self-timed logic for reducing power consumption and increasing and improving processing capabilities is disclosed. The self-timed logic is employed to implement digital signal processors (DSPs) including analog to digital (ADC) signal converters, a state machine or the components of microprocessor cores, e.g., the CPU, arithmetic logic units (ALU), on-chip RAM and ROM and data and control buses, and other logic units, e.g., additional RAM and ROM, a direct memory address (DMA) controller, a block mover/reader, a cyclic redundancy code (CRC) calculator, and certain uplink and downlink telemetry signal processing stages. The self-timed CMOS logic is incorporated into the same IC or ICs with clocked CMOS logic in a manner that minimizes the size of the clock tree serving the clocked CMOS logic, allows for efficient allocation of chip real estate, and provides manufacturing economies.

Claims11

Dependent claims

An implantable medical device for at least one of delivering a therapy to a patient's body and monitoring a physiologic condition of a patient comprising:

a battery to provide battery energy;
and
at least one integrated circuit powered by the battery and providing control and timing functions, said integrated circuit including:
(a) a system clock providing clock signals;
(b) clocked logic circuits responsive to said clock signals to perform defined circuit functions in timed synchrony with said clock signals;
(c) a clock tree that couples said clock signals from said system clock to the clocked logic circuits;
(d) means for sensing a physiologic condition of the patient and providing a physiologic signal;
and
(e) at least one self-timed logic circuit operating independent of said system clock to process the physiologic signal, whereby the clock tree is minimized and clock energy is conserved;
said self-timed logic circuit comprising a signal processor having a plurality of self-timed logic elements formed into a chain, the signal processor receiving the physiologic signal at an input thereof, processing the physiologic signal, and providing the processed physiologic signal at an output after a self-timed logic propagation delay.

7 more elements

An implantable cardiac pacing system for sensing cardiac signals and delivering pacing pulses through pace/sense electrodes situated in one or more heart chambers comprising:

a battery to provide battery energy;
and
at least one integrated circuit powered by the battery and providing control and timing functions, said integrated circuit including:
(a) a system clock providing clock signals;
(b) a clocked logic circuit responsive to a clock signal to time-out a pacing escape interval;
(c) means responsive to time-out of the pacing escape interval for generating and delivering a pacing pulse to the pace/sense electrodes;
(d) a clock tree that couples said clock signals from said system clock to the clocked logic circuit;
(e) means coupled with said pace/sense electrodes for sensing a cardiac signal of the patient and providing a cardiac sensed event signal;
and
(f) at least one self-timed logic circuit operating independent of said system clock to process the sensed event signal, whereby the clock tree is minimized and clock energy is conserved;
said self-timed logic circuit comprising a signal processor coupled with said cardiac signal sensing means and having a plurality of self-timed logic elements formed into a chain, the signal processor receiving the cardiac sensed event signal at an input thereof, processing the cardiac sensed event signal, and providing the processed cardiac sensed event signal at an output after a self-timed logic propagation delay.

8 more elements

Dependencies are inferred from the claim text.

Implantable medical device incorporating self-timed logic

Life of this patent

Implantable medical device incorporating self-timed logic

Life of this patent

Abstract

Claims11