Method and apparatus for a digital video cassette (DVC) decode system

A method of decoding variable length coded data having a plurality of digital interchange format (DIF) sequences including a plurality of DIF blocks comprising:

• formatting contiguously the plurality of DIF blocks to provide contiguous DCT blocks;
• decoding the contiguous DCT blocks to provide run-length amp pairs;
• and
• providing a DIF sequence data storage configured to store a plurality of DIF blocks having a plurality of DCT components wherein the act of formatting contiguously the plurality of DIF blocks includes:
• detecting a complete DCT component from the plurality of DCT components stored in the DIEF sequence data storage;
• storing remaining DCT components to a pass 2 storage register in the DIF sequence data storage;
• detecting complete DCT components from the pass 2 storage register;
• storing incomplete DCT components to a pass 3 storage register in the DIF sequence data storage;
• and
• formatting the DCT components to provide the contiguous DCT blocks from the plurality of DCT components stored in the DIF sequence data storage, the pass 2 storage register, and the pass 3 storage register, respectively.

A computing system having an input and output for transceiving video frames including a plurality of digital interchange format (DIF) sequences, comprising:

• a digital video cassette (DVC) device coupled to the input configured to provide the video frames;
• a concatenation engine configured to receive the video frames and contiguously format a plurality of DIF blocks of a DIF sequence to provide contiguous DCT blocks;
• a run-length amp pair generator coupled to the concatenation engine configured to decode the contiguous DCT blocks to provide run-length amp pairs;
• a video decoder coupled to the run-length amp pair generator configured to decode the run-length amp pairs;
• a display controller coupled to the video decoder configured to display decoded run-length amp pairs;
• and
• a DIF sequence data storage configured to store a plurality of DIF blocks having a plurality of DCT components wherein the concatenation engine includes:
• a pass 1 engine coupled to the DIF sequence data storage to detect a DCT component and store remaining DCT components to a pass 2 storage register of the DIF sequence data storage;
• a pass 2 engine coupled to the pass 2 storage register engine to detect complete DCT components from the remaining DCT components of the pass 2 storage register and store incomplete DCT components to a pass 3 storage register of the DIF sequence data storage;
• and
• a pass 3 engine coupled to the DIF sequence data storage, the pass 2 storage register, and the pass 3 storage register to contiguously format the plurality of DIF components from the DIF sequence data storage to provide the contiguous DCT blocks.

A variable length decode engine operative to receive a video frame having a plurality of digital interchange format (DIF) sequences including a plurality of embedded AC coefficients, comprising:

• a concatenation engine configured to contiguously format a plurality of DIF blocks of a DIF sequence to provide contiguous DCT blocks;
• and
• a run-length amp pair generator coupled to the concatenation engine configured to decode the contiguous DCT blocks to provide run-length amp pairs,
• a DIF sequence data storage configured to store a plurality of DIF blocks having a plurality of DCT components wherein the concatenation engine includes:
• a pass 1 engine coupled to the DIF sequence data storage to detect a DCT component and store remaining DCT components to a pass 2 overflow storage register of the DIF data storage;
• a pass 2 engine coupled to the pass 2 overflow storage register to detect complete DCT components from the remaining DCT components of the pass 2 overflow storage register and store incomplete DCT components to a pass 3 overflow storage register of the DIF sequence data storage;
• and
• a pass 3 engine coupled to the DIF sequence data storage, the pass 2 overflow storage register, and the pass 3 overflow storage register to contiguously format the plurality of DIF components from the DIF sequence data storage, the pass 2 overflow storage register, and the pass 3 overflow storage, respectively to provide the contiguous DCT block, wherein the pass 1 engine, the pass 2 engine, and the pass 3 engine operate in parallel.

A method of decoding variable length coded data having a plurality of digital interchange format (DIF) sequences including a plurality of DIF blocks comprising the steps:

• formatting contiguously the plurality of DIF blocks to provide contiguous DCT blocks;
• and
• decoding the contiguous DCT blocks to provide run-length amp pairs;
• a DIF sequence data storage configured to store a plurality of DIF blocks having a plurality of DCT components wherein the step of formatting contiguously the plurality of DIF blocks includes the steps:
• detecting a complete DCT component from the plurality of DCT components stored in the DIF sequence data storage;
• storing remaining DCT components to a pass 2 storage register in the DIF sequence data storage;
• detecting complete DCT components from the pass 2 storage register;
• storing incomplete DCT components to a pass 3 storage register in the DIF sequence data storage;
• and
• formatting the DCT components to provide the contiguous DCT blocks from the plurality of DCT components stored in the DIF sequence data storage, the pass 2 storage register, and the pass 3 storage register, respectively.

A computing system having an input and output for transceiving video frames including a plurality of digital interchange format (DIF) sequences, comprising:

• a digital video cassette (DVC) device coupled to the input configured to provide the video frames;
• a concatenation engine configured to receive the video frames and contiguously format a plurality of DIF blocks of a DIF sequence to provide contiguous DCT blocks;
• and
• a run-length amp pair generator coupled to the concatenation engine configured to decode the contiguous DCT blocks to provide run-length amp pairs;
• and
• a video decoder coupled to the run-length amp pair generator configured to decode the run-length amp pairs;
• a display controller coupled to the video decoder configured to display decoded run-length amp pairs;
• a DIF sequence data storage configured to store a plurality of DIF blocks having a plurality of DCT components wherein the concatenation engine includes:
• a pass 1 engine coupled to the DIF sequence data storage to detect a DCT component and store remaining DCT components to a pass 2 storage register of the DIF sequence data storage;
• a pass 2 engine coupled to the pass 2 storage register engine to detect complete DCT components from the remaining DCT components of the pass 2 storage register and store incomplete DCT components to a pass 3 storage register of the DIF sequence data storage;
• and
• a pass 3 engine coupled to the DIF sequence data storage, the pass 2 storage register, and the pass 3 storage register to contiguously format the plurality of DIF components from the DIF sequence data storage to provide the contiguous DCT blocks.

A method comprising:

• receiving variable length coded data having a plurality of digital interchange format (DIF) sequences including a plurality of DIF blocks;
• identifying DCT components in a first portion of the variable length coded data during a first pass process;
• and
• enabling a second pass process to pickup where the first pass process left off by saving state information associated with the first pass process in a working buffer and saving unfinished DCT components data in the working buffer, wherein the second pass process identifies DCT components by concentrating the unfinished DCT component data in the working buffer with a second portion of the variable