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US 6,389,095 B1Granted
Divide-by-three circuit
AssigneeQUALCOMM Incorporated
InventorBo Sun
Life of this patent
Estimating the term…
Abstract
An in-phase clock signal CLK_I drives a first pair of connected data flip-flops (DFFs) (302) and (308), with feedback through a NOR gate (310) and output through an in-phase OR gate (320). The output signal OUT_I is a clock signal with a third of the frequency of CLK_I. A quadrature-phase clock signal CLK_Q drives a second pair of (DFFs) (504) and (506), with output through a quadrature OR gate (508). The output signal OUT_Q is a clock signal with a third of the frequency of CLK_Q, and in quadrature with OUT_I.
Claims2
An in-phase divide-by-three circuit, characterized in that it comprises:
- (a) a first data flip-flop (DFF) connected to receive, at a clock input, an in-phase input clock signal having an input frequency;
- (b) a second DFF connected to receive:
- (1) at a clock input, the in-phase input clock signal;
- and
- (2) at a data input, a slave output from the first DFF;
- (c) a NOR gate, connected:
- (1) to receive:
- (A) the slave output signal from the first DFF;
- and
- (B) a slave output signal from the second DFF;
- and
- (2) to apply a NOR output signal to a data input of the first DFF;
- and
- (d) an in-phase OR gate, connected to receive:
- (1) the slave output signal from the first DFF;
- and
- (2) a master output signal from the second DFF;
- whereby an output of the in-phase OR gate produces an output in-phase clock signal having an output frequency equal to one third of the input frequency.
15 more elements
Dependencies are inferred from the claim text.