Digital clock/data signal recovery method and apparatus

A method for recovering a clock signal from a data portion of a received signal, comprising:

• detecting a phase of the data portion of the received signal;
• accumulating a plurality of the detected phases to determine a change in a recovered clock signal;
• selecting one of a plurality of clock signals to be the recovered clock signal, each of the plurality of clock signals having about the same frequency and differing delays, in response to the determined change;
• using the selected clock signal for detecting the phase of the data portion of the received signal by sampling the selected clock signal in response to at least one of a rising or falling edge of a data transition and supplying the sample as the detected phase;
• wherein recovering the clock signal comprises recovering a transmit clock signal from a non-periodic incoming data signal;
• providing from a local oscillator a fixed frequency at substantially a same frequency as the transmit clock signal of the non-periodic data signal;
• providing delayed clock signals of substantially the same frequency from a single frequency of the local oscillator and;
• wherein accumulating and selecting comprises using a phase pump portion connected to the output terminal of a non-linear digital signal processor, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the digital signal processor.

A receiver apparatus for receiving clock and data signals in a digital communications system comprising:

• an equalizing and slicing portion which receives an incoming data signal and outputs a discrete level analog transition time signal;
• a clock recovery portion including:
• a lead/lag detector having two input terminals and an output terminal, a first input terminal being coupled to receive the discrete level analog transition time signal;
• a signal processor having an input terminal coupled to receive an output signal from the phase detector, and an output terminal carrying a signal indicating the amount of lead or lag in the recovered clock signal;
• a selector having a plurality of input terminal respectively coupled to receive clock signals having about the same frequency and having different relative delays, a control terminal coupled to the output terminal of the signal processor, and an output terminal carrying the recovered clock signal, the recovered clock signal being coupled to the second input terminal of the lead/lag detector;
• the lead/lag detector being constructed to provide at the output of the lead/lag detector a sample of the recovered clock signal from the second input terminal of the lead/lag detector in response to at least one of a rising or falling edge of a data transition at the first input of the lead/lag detector;
• wherein the clock recovery portion is constructed so as to be capable of recovering a transmit clock signal from a non-periodic incoming data signal;
• a local oscillator having a fixed frequency at substantially a same frequency as the transmit clock signal of the non-periodic data signal;
• a phase delay circuit coupled between the local oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of the substantially the same frequency from a single frequency of the local oscillator;
• and
• wherein the signal processor comprises a phase pump portion connected to an output terminal of a non-linear digital signal processing portion, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the signal processing portion;
• and
• a data recovery portion having a clock terminal coupled to receive the recovered clock signal, a data input terminal coupled to receive the incoming data signal, and an output terminal providing a recovered data signal.

A clock signal recovery apparatus for use in a receiver in a digital communications system, the clock signal recovery apparatus comprising:

• a) a lead/lag detector comprising first and second input terminals and an output terminal, the first input terminal being adapted to receive a data signal having an embedded clock;
• b) a signal processor comprising an input terminal coupled to the output terminal of the lead/lag detector, the signal processor being capable of providing a control signal at the signal processor output terminal responsive to signals at the output terminal of the lead/lag detector;
• c) a selector having a plurality of input terminals adapted to receive a plurality of phase delayed clock signals, the selector comprising a control terminal coupled to the output terminal of the signal processor, the selector being capable of providing the recovered clock signal at an output terminal in response to the control signal, the output terminal of the selector being coupled to the second input terminal of the lead/lag detector;
• d) the lead/lag detector being constructed to compare at least one of a rising or falling edge of a data transition of the data signal with the reconstructed clock signal and to supply a fixed pulse width output at the output terminal of the lead/lad detector indicating a relative leading or lagging position of edge transitions of the reconstructed clock and the embedded clock, and wherein a leading or lagging indication is supplied only when the at least one of a rising or falling edge is detected at the first input of the lead/lag detector such that the embedded clock signal may be recovered without utilizing a reference clock signal;
• e) wherein the clock recovery apparatus is constructed so as to be capable of recovering the clock signal to be recovered from non-periodic data within the incoming signal;
• f) a local oscillator having a fixed frequency at substantially a same frequency as the clock signal to be recovered;
• g) a phase delay circuit coupled between the local oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of substantially the same frequency from a single frequency of the local oscillator;
• and
• h) wherein the signal processor comprises a phase pump portion connected to an output terminal of a non-linear digital signal processing portion, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the signal processing portion.

A clock signal recovery apparatus for use in a receiver in a digital communications system the clock signal recovery apparatus comprising:

• a phase detector having two input terminals and an output terminal, a first input terminal being coupled to receive an incoming signal having a clock signal to be recovered;
• a signal processor having an input terminal coupled to receive an output signal from the phase detector, and an output terminal carrying a signal indicating a lead or lag in a the recovered clock signal;
• a selector having a plurality of input terminals respectively coupled to receive clock signals of the same frequency and having differing relative delays, a control terminal coupled to the output terminal of the signal processor, and an output terminal carrying the recovered clock signal, the recovered clock signal being coupled to the second input terminal of the phase detector;
• wherein the phase detector is a D type flip-flop having a clock input terminal as the first input terminal and a D input as the second input terminal;
• wherein the clock recovery apparatus is constructed so as to be capable of recovering the clock signal to be recovered from non-periodic data within the incoming signal;
• a local oscillator having a fixed frequency at substantially a same frequency as the clock signal to be recovered;
• a phase delay circuit coupled between the local oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of substantially the same frequency from a single frequency of the local oscillator;
• and
• wherein the signal processor comprises a phase pump portion connected to an output terminal of a non-linear digital signal processing portion, the phase pump portion being capable of providing a latched N-bit output signal in response to signals at the output terminal of the signal processing portion.

A clock signal recovery apparatus for use in a receiver of a digital transmit/receive circuit, the clock signal recovery apparatus comprising:

• a D-flip flop having a clock input terminal adapted to receive an incoming data signal;
• a non-linear digital signal processor having an input terminal coupled to receive an output signal from the D-flip flop, the non-linear digital signal processor being capable of outputting at an output terminal;
• a phase pump connected to the output terminal of the non-linear digital signal processor, the phase pump being capable of providing a latched N-bit output signal in response to the output terminal of the signal processor;
• a selector having a plurality of input terminals respectively coupled to receive clock signals of the same frequency and having differing relative delays, a control terminal coupled to the output terminal of the signal processor, and an output terminal carrying the recovered clock signal, the recovered clock signal being coupled to the second input terminal of the lead/lag detector;
• a lead/lag detector being constructed to provide at the output of the lead/lag detector a sample of the recovered clock signal from the second input terminal of the lead/lag detector in response to at least one of a rising or falling edge of a data transition at the first input of the lead/lag detector, the lead/lag detector comprising the D-flip flop;
• wherein the clock recovery apparatus is constructed so as to be capable of recovering the clock signal from non-periodic data within the incoming data signal;
• a local transmitter oscillator having a fixed frequency at substantially a same frequency as a transmit clock signal of the non-periodic data signal;
• and
• a phase delay circuit coupled between the local transmitter oscillator and the selector, the phase delay circuit being capable of providing delayed clock signals of substantially the same frequency from a single frequency of the local transmitter oscillator.