US 6,389,088 B1 · Synchronization and tracking in a digital communication system

Abstract

There is disclosed a bit sync search and frame sync search system operative with a digital data signal as transmitted by a digital radio transmitter. The bit search is implemented by detecting a predetermined phasing signal which is incorporated in the digital signal and which has a repetitive bit pattern of ones and zeroes. The phasing signal is first detected by providing an in-phase and quadrature component signal and correlating those signals to provide an output signal indicative of the bit pattern in the phasing signal. After the phasing signal has been provided and an oscillator associated with a receiving apparatus is compensated according to the detected phasing signal, a tracking mode is entered, whereby a frame signal is captured and the system generates histograms of data bit transitions for producing an error signal indicative of the difference of the transmitted clock rate and the sampling portion of a received bit. In this manner, by adjusting the clock according to the error signal produced by the histogram process one can be assured that the sampling rate at the receiver will occur relatively at the center of each bit to therefore provide reliable decoding or detection of the received digital data signal in the presence of the noise.

Claims6

Dependent claims

In a receiver of a digital communication system, a method of detecting a periodic synchronization signal having a bit synchronization pattern, the method comprising the steps of:

(a) accumulating a set of samples during a frame;
(b) computing an inphase correlation value and a quadrature correlation value for the set of samples;
(c) computing a partial power for the set of samples;
(d) repeating steps (a), (b) and (c) for a plurality of frames;
(e) computing an inphase sum from the inphase correlation values of the plurality of frames and a quadrature sum from the quadrature correlation values of the plurality of frames;
(f) computing a signal power as the sum of the squares of the inphase sum and quadrature sum;
(g) computing a total power as the sum of the partial powers of the plurality of frames;
and
(h) declaring a detection of the periodic synchronization signal by said receiver if the signal power is above a minimum threshold and greater than a required percentage of the total power.

6 more elements

A digital communication system, comprising:

a transmitter configured to transmit a periodic synchronization signal having a bit synchronization pattern;
and
a receiver configured to detect the periodic synchronization signal, said receiver comprising:
an analog-to-digital (A/D) converter that periodically samples data bits of a received signal to accumulate a set of samples for each of a plurality of frames;
and
a processor adapted to compute:
an inphase correlation value, a quadrature correlation value and a partial power for each frame from the set of samples corresponding to the frame;
an inphase sum from the inphase correlation values of the plurality of frames;
a quadrature sum from the quadrature correlation values of the plurality of frames;
a signal power as the sum of the squares of the inphase sum and quadrature sum;
and a total power as the sum of the partial powers of the plurality of frames;
said processor declaring a detection of the periodic synchronization signal if the signal power is above a minimum threshold and greater than a required percentage of the total power.

9 more elements

Dependencies are inferred from the claim text.

Synchronization and tracking in a digital communication system

Life of this patent

Synchronization and tracking in a digital communication system

Life of this patent

Abstract

Claims6