Trellis decoder
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorMichiru Hori
Life of this patent
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Abstract
A Trellis decoder in which a demodulated signal is handled by dividing into four areas for eight symbols, namely a pre-circuit obtains a 3-bit sign according to a high-order 4-bit sign in the demodulated signal; an area determining circuit identifies any of the four areas by obtaining a 2-bit sign in the 3-bit output from the pre-circuit; a delay circuit delays the 2-bit output from the area determining circuit and a sign for the MSB in the demodulated signal; and a selection circuit identifies a value of a high-order two bits in a received symbol according to the 2-bit output of the area determining circuit, the MSB in the demodulated signal, and an estimated value of the LSB in the received symbol outputted by a convolutional coder.
Claims5
A Trellis decoder for demodulating a signal with a symbol therein subjected to modulation for trellis coding in a transmitting side to a signal expressed with N-bit two-valued signs (N:
- natural number not less than 4) for each of the I axis and Q axis and correcting an error in a received symbol expressed with an X-bit sign from a most significant bit to a X-th bit (X:
- natural number not less than 3 and smaller than N) from the high order bit in the demodulated signal, said Trellis decoder comprising:
- a pre-circuit for outputting any of “X-power of 2” number of signs each expressed with X bits and different from each other according to a sign for “X+1” bits from the most significant bit to the “X+1”th bit from the high order bit in the demodulated signal;
- an area determining circuit for outputting any of “(X−1) power of 2” number of signs each expressed with “X−1” bits and different from each other according to a sign expressed with any X bits outputted from said pre-circuit;
- a Viterbi decoder for correcting an error for a value of a sign for a least significant bit in the received symbol;
- a convolutional coder for executing recoding according to a result of error correction by said Viterbi decoder and outputting an estimated value of a sign for the least significant bit in the received symbol obtained by the operation for convolution;
- a selection circuit for identifying a value of a sign for the “X−1” bit from the most significant bit to the “X−1”th bit from the high order bit in the received symbol according to a sign of “X+1” bits consisting of a sign of any “X−1” bits outputted from said area determining circuit, a sign of the most significant bit in the received symbol, and a 1-bit sign outputted from said convolutional coder;
- and
- a delay circuit for receiving a sign for any “X−1” bits outputted from said area determining circuit and a sign for the most significant bit in the demodulated signal and inputting a sign for the X bits as a total of the bits above into said selection circuit in synchronism to the 1-bit sign outputted from said convolutional coder.
Dependencies are inferred from the claim text.