Method and apparatus for preventing memory overrun in a data transmission system

A method for preventing memory overrun in a packet based data transmission system including a high level data link control (HDLC) controller having a receive buffer, a processor, and a random access memory (RAM) shared by the HDLC controller and the processor, the method comprising:

• initializing a communication channel between the HDLC controller and a user through a PCM bus;
• transferring data from the user to the receive buffer and from the receive buffer to a first buffer in RAM;
• receiving a set of reception termination instructions at the HDLC controller;
• sending an acknowledge instruction to the processor for each reception termination instruction received by the HDLC controller;
• terminating data reception between the HDLC controller and the user;
• and
• transferring data to a second buffer created in the RAM responsive to receiving acknowledge instruction after terminating data reception between the HDLC controller and the user.

A packet based data transmission system, comprising:

• a memory having a first buffer and a plurality of descriptor registers;
• an interface device coupled to the memory and adapted to receive packetized data from a user through a pulse code modulation bus, and transfer the packetized data from a receive buffer in the interface device to the first buffer;
• and
• a central processing unit (CPU) coupled to the memory and the interface device adapted to terminate data reception at the interface device, to receive data reception termination acknowledgement from the interface device, to create a second buffer in the memory responsive to receiving the data reception termination acknowledgement, and to make the plurality of descriptor registers in the memory point to the second memory buffer such that transfers of packetized data from the interface device to the memory occurring after the termination of data reception write to the second buffer.