Semiconductor memory device outputting data according to a first internal clock signal and a second internal clock signal
AssigneeFujitsu Limited
InventorTadao Aikawa
Life of this patent
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Abstract
A semiconductor memory device outputs data in synchronization with an external clock signal. The semiconductor memory device comprises a first frequency divider dividing a frequency of the external clock signal supplied thereto so as to generate a first internal clock signal; a delay circuit delaying the external clock signal; a second frequency divider dividing a frequency of a signal supplied from the delay circuit so as to generate a second internal clock signal; and a data control unit outputting the data according to the first internal clock signal and the second internal clock signal.
Claims7
A semiconductor memory device for outputting data in synchronization with an external clock signal, the device comprising:
- a first frequency divider dividing a frequency of the external clock signal supplied thereto so as to generate a first internal clock signal;
- a delay circuit delaying said external clock signal;
- a second frequency divider dividing a frequency of a signal supplied from said delay circuit so as to generate a second internal clock signal;
- and
- a data control unit outputting the data according to said first internal clock signal and said second internal clock signal.
A semiconductor memory device having a clock buffer buffering an external clock signal supplied thereto, and a data control unit outputting predetermined data according to a data control signal supplied thereto, the device outputting said data in synchronization with said external clock signal, the device comprising:
- a delay circuit delaying a signal generated by said clock buffer;
- a first frequency divider dividing a frequency of said signal generated by said clock buffer so as to generate a first internal clock signal;
- a second frequency divider dividing a frequency of a signal supplied from said delay circuit so as to generate a second internal clock signal;
- and
- an output control unit generating said data control signal according to said first internal clock signal and said second internal clock signal.
Dependencies are inferred from the claim text.