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US 6,388,942 B1Granted
Deep pipe synchronous SRAM
AssigneeCypress Semiconductor Corporation
InventorPurushothaman Ramakrishnan
Life of this patent
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Abstract
An apparatus configured to store and present data. The apparatus may comprise a plurality of storage elements configured to store one or more wordline signals. Each of the plurality of storage elements may be implemented within a memory cell.
Claims20
An apparatus configured to store and present data, said apparatus comprising:
- a memory core comprising a plurality of memory cells arranged in columns and rows;
- a plurality of storage elements configured to store one or more wordline signals, wherein each of said plurality of storage elements is implemented within a column of said memory core.
An apparatus comprising:
- means for storing and presenting data comprising a plurality of memory cells arranged in columns and rows;
- and
- means for storing one or more wordline signals implemented within a column of said means for storing and presenting data.
A method for providing a deep pipe synchronous memory comprising the steps of:
- (A) storing a first value in a first stage of a pipeline in response to a clock signal;
- (B) storing one or more second values in one or more intermediate stages of said pipeline in response to said first value and said clock signal;
- and
- (C) storing a third value in a last stage of said pipeline in response to one or more of said second values and said clock signal, wherein said last stage of said pipeline is implemented within a column of a memory core.
1 more element
Dependencies are inferred from the claim text.